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authorAngel Pons <th3fanbus@gmail.com>2021-01-20 01:32:17 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-02-10 07:29:29 +0000
commita8df6cff16d4f24a7f6dfedd5979d0948ddda189 (patch)
tree949d112b6fb9ec868200dfb57869d2f3b0fb6b59 /src/northbridge/intel/ironlake/acpi
parentd9e58dca9e72ca2efa62eab832aad606c9c58fcd (diff)
nb/intel/ironlake: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I166dbebf0eaf9fe0454145d4d48a0622743916fd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/ironlake/acpi')
-rw-r--r--src/northbridge/intel/ironlake/acpi/hostbridge.asl2
-rw-r--r--src/northbridge/intel/ironlake/acpi/ironlake.asl6
2 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/ironlake/acpi/hostbridge.asl b/src/northbridge/intel/ironlake/acpi/hostbridge.asl
index d6a2cf8d2f..62ca81a425 100644
--- a/src/northbridge/intel/ironlake/acpi/hostbridge.asl
+++ b/src/northbridge/intel/ironlake/acpi/hostbridge.asl
@@ -48,7 +48,7 @@ Device (MCHC)
Name (CTCD, 1) /* CTDP Down Select */
Name (CTCU, 2) /* CTDP Up Select */
- OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000)
+ OperationRegion (MCHB, SystemMemory, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x8000)
Field (MCHB, DWordAcc, Lock, Preserve)
{
Offset (0x5930),
diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl
index 31af469345..098dd13ab8 100644
--- a/src/northbridge/intel/ironlake/acpi/ironlake.asl
+++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl
@@ -11,9 +11,9 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
- Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000)
- Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
- Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
+ Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00008000)
+ Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
+ Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH