diff options
author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 14:03:44 +0100 |
---|---|---|
committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-30 23:12:23 +0000 |
commit | b274ec73ab608384c925876d5a3bcf0396dcc3d5 (patch) | |
tree | 1eede7603565a8dc1dda075c4aa8b072f5c111c8 /src/northbridge/intel/ironlake/acpi.c | |
parent | 10f9b83f534bdc89e00f0a02befd952ae8d7f829 (diff) |
nb/intel/ironlake: Use MMCONF_BUS_NUMBER everywhere
Bootblock enabling needs some special handling. Also, the definition of
the `get_pcie_bar` function is incorrect for Ironlake, so remove it.
With this patch, using 64 and 128 for MMCONF_BUS_NUMBER should work.
However, it has not been tested. Using 256 busses should still work.
Change-Id: Ic466ddc7b80f60af5cbff53583281440f02974c7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49761
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/ironlake/acpi.c')
-rw-r--r-- | src/northbridge/intel/ironlake/acpi.c | 46 |
1 files changed, 3 insertions, 43 deletions
diff --git a/src/northbridge/intel/ironlake/acpi.c b/src/northbridge/intel/ironlake/acpi.c index 688dd5fd81..97676e7cbb 100644 --- a/src/northbridge/intel/ironlake/acpi.c +++ b/src/northbridge/intel/ironlake/acpi.c @@ -1,52 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#define __SIMPLE_DEVICE__ - -#include <types.h> -#include <commonlib/helpers.h> -#include <device/device.h> -#include <device/pci_ops.h> +#include <acpi/acpi.h> #include "ironlake.h" -static int decode_pcie_bar(u32 *const base, u32 *const len) -{ - *base = 0; - *len = 0; - - const u32 pciexbar_reg = pci_read_config32(QPI_SAD, SAD_PCIEXBAR); - - if (!(pciexbar_reg & (1 << 0))) - return 0; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: /* 256MB */ - *base = pciexbar_reg & (0x0f << 28); - *len = 256 * MiB; - return 1; - case 1: /* 128M */ - *base = pciexbar_reg & (0x1f << 27); - *len = 128 * MiB; - return 1; - case 2: /* 64M */ - *base = pciexbar_reg & (0x3f << 26); - *len = 64 * MiB; - return 1; - } - - return 0; -} - unsigned long acpi_fill_mcfg(unsigned long current) { - u32 length, pciexbar; - - if (!decode_pcie_bar(&pciexbar, &length)) - return current; - - const int max_buses = length / MiB; - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - pciexbar, 0x0, 0x0, max_buses - 1); + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); return current; } |