diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2010-05-14 19:09:20 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2010-05-14 19:09:20 +0000 |
commit | bf264e940e3c97b3924a2361b7149f8533f400b4 (patch) | |
tree | b7296417cb77d61c15585b89c3dca866c8fb05b3 /src/northbridge/intel/i945/udelay.c | |
parent | cbac4981be1e485a2bab731338694d13cb768296 (diff) |
i945:
* fix some potential compiler issues with newer gccs
* add some more comments
* make 32bit accesses for feature test functions
* make some objects drivers because they contain a pci_driver struct.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i945/udelay.c')
-rw-r--r-- | src/northbridge/intel/i945/udelay.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 965c890d1b..d5349c937e 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <delay.h> #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> @@ -24,7 +25,7 @@ * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock */ -static void udelay(u32 us) +void udelay(u32 us) { u32 dword; tsc_t tsc, tsc1, tscd; |