diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2016-11-19 15:46:42 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-29 17:16:14 +0100 |
| commit | 2966c9958985ed5a856f9aa6cfdb6dfa45ea8bf9 (patch) | |
| tree | b203b329293eff8846f2fa8be27953cddcc1a9db /src/northbridge/intel/i945/gma.c | |
| parent | ca387539b540fb4cbf4f4c2be860d6d8a752b7e5 (diff) | |
nb/intel/sandybridge/raminit: Support CL > 11
The code won't allow anything beyond CL11 due to short
CAS Latency mask and a bug in mr0 which had the wrong
bit set for CL > 11.
Increase the CAS bitmask, fix the mr0 reg to allow CAS Latencies
from CL 5 to CL 18.
Use defines instead of hardcoding min and max CAS latencies.
Tested on X220 with two 1866 MHz, CL13 memories
Tested-By: Nicola Corna <nicola@corna.info>
Change-Id: I576ee20a923fd63d360a6a8e86c675dd069d53d6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17502
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge/intel/i945/gma.c')
0 files changed, 0 insertions, 0 deletions