diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/northbridge/intel/i945/early_init.c | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel/i945/early_init.c')
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 1913b524a5..7ab252585a 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -93,7 +93,7 @@ static void i945m_detect_chipset(void) } printk(BIOS_DEBUG, "\n"); - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); } @@ -143,7 +143,7 @@ static void i945_detect_chipset(void) } printk(BIOS_DEBUG, "\n"); - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); } @@ -237,7 +237,7 @@ static void i945_setup_egress_port(void) /* Egress Port Virtual Channel 1 Configuration */ reg32 = EPBAR32(0x2c); reg32 &= 0xffffff00; - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { if ((MCHBAR32(CLKCFG) & 7) == 0) reg32 |= 0x1a; /* 1067MHz */ } @@ -256,7 +256,7 @@ static void i945_setup_egress_port(void) reg32 |= (0x0a << 16); EPBAR32(EPVC1RCAP) = reg32; - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { if ((MCHBAR32(CLKCFG) & 7) == 0) { /* 1067MHz */ EPBAR32(EPVC1IST + 0) = 0x01380138; EPBAR32(EPVC1IST + 4) = 0x01380138; @@ -941,14 +941,14 @@ void i945_late_initialization(int s3resume) i945_setup_dmi_rcrb(); - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) i945_setup_pci_express_x16(); i945_setup_root_complex_topology(); -#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if !CONFIG(HAVE_ACPI_RESUME) #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) sdram_dump_mchbar_registers(); { |