diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 12:32:22 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-10 07:30:05 +0000 |
| commit | 4299cb48294af6940a6823696d346fd5ee1bac4e (patch) | |
| tree | 25d24b083daacdb74ea754c16531d69b61a925bd /src/northbridge/intel/i945/early_init.c | |
| parent | e88f705946a1f8b18ff421c654a568581b1e969e (diff) | |
nb/intel/i945: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Getac P470 remains identical.
Change-Id: If6d6cba76bdd1134372ab2faa475e574fdc5fddf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/i945/early_init.c')
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 4564ff4bbb..b91afda187 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -143,9 +143,9 @@ static void i945_setup_bars(void) printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); + pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1); /* vram size from CMOS option */ @@ -715,7 +715,7 @@ static void i945_setup_root_complex_topology(void) EPBAR32(EPLE1D) |= (1 << 16) | (1 << 0); - EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; + EPBAR32(EPLE1A) = CONFIG_FIXED_DMIBAR_MMIO_BASE; EPBAR32(EPLE2D) |= (1 << 16) | (1 << 0); @@ -734,11 +734,11 @@ static void i945_setup_root_complex_topology(void) DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0); - DMIBAR32(DMILE2A) = DEFAULT_EPBAR; + DMIBAR32(DMILE2A) = CONFIG_FIXED_EPBAR_MMIO_BASE; /* PCI Express x16 Port Root Topology */ if (pci_read_config8(HOST_BRIDGE, DEVEN) & DEVEN_D1F0) { - pci_write_config32(p2peg, LE1A, DEFAULT_EPBAR); + pci_write_config32(p2peg, LE1A, CONFIG_FIXED_EPBAR_MMIO_BASE); pci_or_config32(p2peg, LE1D, 1 << 0); } } @@ -751,7 +751,7 @@ static void ich7_setup_root_complex_topology(void) RCBA32(ULD) |= (1 << 24) | (1 << 16); - RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR; + RCBA32(ULBA) = CONFIG_FIXED_DMIBAR_MMIO_BASE; /* Write ESD.CID to TCID */ RCBA32(RP1D) |= (2 << 16); RCBA32(RP2D) |= (2 << 16); |