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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-07-01 11:21:53 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-07-04 00:53:39 +0200 |
commit | 032c23db08e6f0c6a2937092edafa26339aa4921 (patch) | |
tree | a2b840787cb06d3896524e19ffbeef709abfd965 /src/northbridge/intel/i945/early_init.c | |
parent | fbdb085549b6c500e12dc2fb21143a197b4be042 (diff) |
intel/i945: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on all boards
with i945 chipset. To enable MMIO style access, add explicit
PCI IO config write in the bootblock.
Change-Id: Ia1ab73f1a2dcda87db4eb9b2ffddc6f7b4382b01
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3584
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Diffstat (limited to 'src/northbridge/intel/i945/early_init.c')
-rw-r--r-- | src/northbridge/intel/i945/early_init.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d91930fe16..fd9f6b79b1 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -173,7 +173,6 @@ static void i945_setup_bars(void) /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); |