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authorPatrick Georgi <patrick.georgi@coresystems.de>2010-10-01 08:02:45 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-10-01 08:02:45 +0000
commit77d6683edd1c0af74e4435cf432a558df3fe71eb (patch)
tree496faa30bc4392f2cd9834882564fafc310061b1 /src/northbridge/intel/i945/Kconfig
parent66d1687b927a94991233d1ee87dc916fb6ae033f (diff)
Move several i945 config #defines from romstage.c to Kconfig.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i945/Kconfig')
-rw-r--r--src/northbridge/intel/i945/Kconfig38
1 files changed, 38 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 952bd9ed68..cee1a8745d 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -26,3 +26,41 @@ config FALLBACK_VGA_BIOS_ID
default "8086,27a2"
depends on NORTHBRIDGE_INTEL_I945
+choice
+ default I945GM
+ depends on NORTHBRIDGE_INTEL_I945
+ help
+ Different i945 variants require slightly different setup.
+
+config I945GM
+ bool "i945GM (Mobile) chipset"
+
+config I945GC
+ bool "i945GC chipset"
+
+endchoice
+
+config CHANNEL_XOR_RANDOMIZATION
+ bool
+ default n
+ depends on NORTHBRIDGE_INTEL_I945
+
+config OVERRIDE_CLOCK_DISABLE
+ bool
+ default n
+ depends on NORTHBRIDGE_INTEL_I945
+ help
+ Usually system firmware turns off system memory clock
+ signals to unused SO-DIMM slots to reduce EMI and power
+ consumption.
+ However, some boards do not like unused clock signals to
+ be disabled.
+
+config MAXIMUM_SUPPORTED_FREQUENCY
+ int
+ default 0
+ depends on NORTHBRIDGE_INTEL_I945
+ help
+ If non-zero, this designates the maximum DDR frequency
+ the board supports, despite what the chipset should be
+ capable of.