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authorStefan Reinauer <stepan@coresystems.de>2010-04-27 06:56:47 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-27 06:56:47 +0000
commit14e22779625de673569c7b950ecc2753fb915b31 (patch)
tree14a6ed759e116e9e6e9bbd7f499b74b96d6cc072 /src/northbridge/intel/i82810/raminit.h
parent0e1e8065e303030c39c3f2c27e5d32ee58a16c66 (diff)
Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i82810/raminit.h')
-rw-r--r--src/northbridge/intel/i82810/raminit.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/i82810/raminit.h b/src/northbridge/intel/i82810/raminit.h
index 5a06dd171d..8c558a5699 100644
--- a/src/northbridge/intel/i82810/raminit.h
+++ b/src/northbridge/intel/i82810/raminit.h
@@ -27,7 +27,7 @@
/* DIMM0 is at 0x50, DIMM1 is at 0x51. */
#define DIMM_SPD_BASE 0x50
-/* The following table has been bumped over to this header to avoid clutter in
+/* The following table has been bumped over to this header to avoid clutter in
* raminit.c. It's used to translate the value read from SPD Byte 31 to a value
* the northbridge can understand in DRP, aka Rx52[7:4], [3:0]. Where most
* northbridges have some sort of simple calculation that can be done for this,
@@ -38,7 +38,7 @@
/* TODO: Find a better way of doing this. */
static const uint8_t translate_spd_to_i82810[] = {
- /* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB
+ /* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB
* side can't be either, at least for now.
*/
/* TODO: For above case, only use the other side if > 4MB, and get some