diff options
| author | Ed Swierk <eswierk@arastra.com> | 2008-03-16 23:36:00 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2008-03-16 23:36:00 +0000 |
| commit | a9faea8977cae2c1c55b83b214aee6845de1c885 (patch) | |
| tree | 3d8545f7fd12062a8177fd7f705f290b2d2c3e7f /src/northbridge/intel/i3100/raminit.h | |
| parent | aaea11b749ccd481a37424c38625873c231f850d (diff) | |
This patch implements support for the Intel 3100 integrated
northbridge and RAM controller.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i3100/raminit.h')
| -rw-r--r-- | src/northbridge/intel/i3100/raminit.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/src/northbridge/intel/i3100/raminit.h b/src/northbridge/intel/i3100/raminit.h new file mode 100644 index 0000000000..abaaa1e30f --- /dev/null +++ b/src/northbridge/intel/i3100/raminit.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* This code is based on src/northbridge/intel/e7520/raminit.h */ + +#ifndef NORTHBRIDGE_INTEL_I3100_RAMINIT_H +#define NORTHBRIDGE_INTEL_I3100_RAMINIT_H + +#define DIMM_SOCKETS 4 +struct mem_controller { + u32 node_id; + device_t f0, f1, f2, f3; + u16 channel0[DIMM_SOCKETS]; + u16 channel1[DIMM_SOCKETS]; +}; + +#endif |