diff options
| author | Bill XIE <persmule@hardenedlinux.org> | 2023-01-29 09:55:19 +0800 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2023-02-02 07:02:10 +0000 |
| commit | b184e6e0a1ccd1d2cb2cc53d06f7969c98cca899 (patch) | |
| tree | 03b2e6220e1292e355c52defd5b2ba2b3a0db52a /src/northbridge/intel/haswell | |
| parent | 2ff381d0d6fce6c2c8bcedb30fe6a908e3a5311b (diff) | |
nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw
Use acpi_create_dmar_ds_ioapic_from_hw() to generate DMAR entries.
This can restore s3 resume capability for Sandy Bridge platforms lost
after commit d165357ec37c ("sb,soc/intel: Use
register_new_ioapic_gsi0()").
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72513
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/haswell')
| -rw-r--r-- | src/northbridge/intel/haswell/acpi.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 290dc1e928..8d179aaa62 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <acpi/acpi.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci_ops.h> #include "haswell.h" @@ -38,8 +39,9 @@ static unsigned long acpi_fill_dmar(unsigned long current) const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, - PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, + PCH_IOAPIC_PCI_BUS, + PCH_IOAPIC_PCI_SLOT, 0); size_t i; for (i = 0; i < 8; ++i) |