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authorMatt DeVillier <matt.devillier@puri.sm>2019-06-15 16:42:00 -0500
committerMartin Roth <martinroth@google.com>2019-06-28 19:11:03 +0000
commit85d3b40a19358c4014eceaea3204feece8b15edd (patch)
tree0542a1debf5d4fed418337d18702461b2c332b8e /src/northbridge/intel/haswell
parent16a70c3d40db0d31d8b6c6c13603d27ad6bf5be3 (diff)
soc/intel/cannonlake: fix use of legacy 8254 timer
FSP sets the use of the 8254 timer via the Enable8254ClockGating UPD, which defaults to enabled, overriding what is set by coreboot. Per the FSP integration guide, this UPD needs to be disabled when a legacy OS is booted (ie, when SeaBIOS is used as the payload). Add a Kconfig option to set the UPD properly based on payload selection, and remove the existing coreboot code in lpc.c since it is either ineffective or being overridden by FSP. Test: build/boot out-of-tree WHL board with both SeaBIOS and Tianocore, ensure 8254 timer usage set correctly for each. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I0e888bf754cb72093f14fc02f39bddcd6d288203 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/haswell')
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