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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-02-12 12:00:40 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-20 23:20:34 +0000 |
| commit | 7be74dbb38e41534055dbb27837e61f480c7db56 (patch) | |
| tree | 03e80d9b65f1fdc17463b55e4d6c5dfa140dde64 /src/northbridge/intel/haswell | |
| parent | cb304c1d85ff0a289c8a7244bf6e8adac07cd624 (diff) | |
nb/x4x/raminit_ddr2: Refactor clock configuration slightly
The result is shorter and (IMHO) more readable code.
Change-Id: Ic51c05d7aa791250d775bd7a640213065d4caba0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/northbridge/intel/haswell')
0 files changed, 0 insertions, 0 deletions