diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-08-28 02:02:00 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-04 23:53:51 +0000 |
| commit | 6c49f40b6e6342b7acb47cb0a57fa10269e3d4c9 (patch) | |
| tree | 76063a89a7e8248c7f757201f2cf2f8a2fcef228 /src/northbridge/intel/haswell | |
| parent | 35597435d023150d847ec11019cb19cba29397bf (diff) | |
haswell: Add Intel TXT support in romstage
Provide necessary romstage hooks to allow unblocking the memory with
SCLEAN. Note that this is slow, and took four minutes with 4 GiB of RAM.
Tested on Asrock B85M Pro4 with tboot. When Linux has tboot support
compiled in, booting as well as S3 suspend and resume are functional.
However, SINIT will TXT reset when the iGPU is enabled, and using a dGPU
will result in DMAR-related problems as soon as the IOMMU is enabled.
However, SCLEAN seems to hang sometimes. This may be because the AP
initialization that reference code does before SCLEAN is missing, but
the ACM is still able to unblock the memory. Considering that SCLEAN is
critical to recover an otherwise-bricked platform but is hardly ever
necessary, prefer having a partially-working solution over none at all.
Change-Id: I60beb7d79a30f460bbd5d94e4cba0244318c124e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/haswell')
| -rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 5b025eba24..3227c02287 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -4,11 +4,14 @@ #include <console/console.h> #include <cf9_reset.h> #include <device/device.h> +#include <device/mmio.h> #include <timestamp.h> #include <cpu/x86/lapic.h> #include <cbmem.h> #include <commonlib/helpers.h> #include <romstage_handoff.h> +#include <security/intel/txt/txt.h> +#include <security/intel/txt/txt_register.h> #include <cpu/intel/haswell/haswell.h> #include <northbridge/intel/haswell/chip.h> #include <northbridge/intel/haswell/haswell.h> @@ -108,12 +111,27 @@ void mainboard_romstage_entry(void) report_platform_info(); + if (CONFIG(INTEL_TXT)) + intel_txt_romstage_init(); + copy_spd(&pei_data); sdram_initialize(&pei_data); timestamp_add_now(TS_AFTER_INITRAM); + if (CONFIG(INTEL_TXT)) { + printk(BIOS_DEBUG, "Check TXT_ERROR register after MRC\n"); + + intel_txt_log_acm_error(read32((void *)TXT_ERROR)); + + intel_txt_log_spad(); + + intel_txt_memory_has_secrets(); + + txt_dump_regions(); + } + post_code(0x3b); intel_early_me_status(); |