Rename ECAM-specific MMCONF Kconfigs

Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space.  Some platforms have a different way of mapping the PCI config
space to memory.  This patch renames the following configs to
make it clear that these configs are ECAM-specific:

- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH

Please refer to CB:57861 "Proposed coreboot Changes" for more
details.

BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
     Make sure Jenkins verifies that builds on other boards

Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

4 files changed, 10 insertions, 10 deletions

diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 61c201a1cb..50acb09a91 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -32,10 +32,10 @@ config VGA_BIOS_ID
 	string
 	default "8086,0166"
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0xf0000000
 
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
 	int
 	default 64
 
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index 7dfae9fa94..513e960a09 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -125,7 +125,7 @@ Name (MCRS, ResourceTemplate()
 			0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
 			0x00010000,,, FSEG)
 
-	// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
+	// PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS)
 	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 			Cacheable, ReadWrite,
 			0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -161,7 +161,7 @@ Method (_CRS, 0, Serialized)
 	}
 
 	PMIN = Local0
-	PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1
+	PMAX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1
 	PLEN = (PMAX - PMIN) + 1
 
 	Return (MCRS)
@@ -178,7 +178,7 @@ Device (PDRC)
 		Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, MCH_BASE_SIZE)
 		Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE)
 		Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE)
-		Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
+		Memory32Fixed (ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
 		Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // TXT
 		Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // TPM
 		Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c
index 1336582889..03a715fa63 100644
--- a/src/northbridge/intel/haswell/bootblock.c
+++ b/src/northbridge/intel/haswell/bootblock.c
@@ -9,7 +9,7 @@
 
 static uint32_t encode_pciexbar_length(void)
 {
-	switch (CONFIG_MMCONF_BUS_NUMBER) {
+	switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
 		case 256: return 0 << 1;
 		case 128: return 1 << 1;
 		case  64: return 2 << 1;
@@ -21,15 +21,15 @@ void bootblock_early_northbridge_init(void)
 {
 	/*
 	 * The "io" variant of the config access is explicitly used to setup the
-	 * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all
+	 * PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all
 	 * subsequent non-explicit config accesses use MCFG. This code also assumes
 	 * that bootblock_northbridge_init() is the first thing called in the non-asm
 	 * boot block code. The final assumption is that no assembly code is using the
-	 * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
+	 * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
 	 *
 	 * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
 	 */
-	const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+	const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
 	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
 	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
 }
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
index 338b4d0c41..f71d1173e3 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
@@ -349,7 +349,7 @@ void perform_raminit(const int s3resume)
 		.mchbar			= CONFIG_FIXED_MCHBAR_MMIO_BASE,
 		.dmibar			= CONFIG_FIXED_DMIBAR_MMIO_BASE,
 		.epbar			= CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar		= CONFIG_MMCONF_BASE_ADDRESS,
+		.pciexbar		= CONFIG_ECAM_MMCONF_BASE_ADDRESS,
 		.smbusbar		= CONFIG_FIXED_SMBUS_IO_BASE,
 		.hpet_address		= CONFIG_HPET_ADDRESS,
 		.rcba			= CONFIG_FIXED_RCBA_MMIO_BASE,