diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 21:31:17 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-12 10:08:09 +0000 |
| commit | 1be9f5841dabd42a740fe23a77ea128fa8d0835d (patch) | |
| tree | fc6fc827590eb83ca9ceea1091b65c123a37f045 /src/northbridge/intel/haswell/romstage.c | |
| parent | 6c8e4dd87b334140b0b30420389931caec3c1c22 (diff) | |
haswell: Introduce ENABLE_DDR_2X_REFRESH Kconfig option
This Kconfig symbol allows doubling the memory's refresh rate, assuming
that the MRC actually cares about it. It is disabled by default except
on the mainboards which explicitly enabled this setting in `pei_data`.
Change-Id: I6318dad0350d1c506c67f9d117d0ae8dad871281
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/northbridge/intel/haswell/romstage.c')
| -rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index ca948132b3..42a2a56c66 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -52,6 +52,7 @@ void mainboard_romstage_entry(void) .gpiobase = DEFAULT_GPIOBASE, .temp_mmio_base = 0xfed08000, .tseg_size = CONFIG_SMM_TSEG_SIZE, + .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), .max_ddr3_freq = 1600, }; |