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authorAngel Pons <th3fanbus@gmail.com>2020-10-13 21:44:08 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-10-23 18:09:32 +0000
commit6791ad221be29d079eeb484edd01089e19f16026 (patch)
treec5d82b852b66aa0222c59e31fba9e82778e93d9a /src/northbridge/intel/haswell/registers
parent6fe7986daf7d7915f27b2e30aa120fce7d834c6e (diff)
nb/intel/haswell: Make MAD_DIMM_* registers indexed
This allows using the macro in a loop, for instance. Change-Id: Ice43e5db9b4244946afb7f3e55e0c646ac1feffb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/haswell/registers')
-rw-r--r--src/northbridge/intel/haswell/registers/mchbar.h4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index d6e59abe02..60e16e0b98 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -5,9 +5,7 @@
/* Register definitions */
#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */
-#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */
-#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */
-#define MAD_DIMM_CH2 0x500c /* Address Decode Channel 2 (unused on HSW) */
+#define MAD_DIMM(ch) (0x5004 + (ch) * 4)
#define MC_INIT_STATE_G 0x5030
#define MRC_REVISION 0x5034 /* MRC Revision */