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authorJohnny Lin <johnny_lin@wiwynn.com>2021-01-25 15:00:48 +0800
committerPatrick Georgi <pgeorgi@google.com>2021-01-28 09:30:09 +0000
commitca083db4d377cdfeca61ad97b33efadc0f9ccf36 (patch)
tree8f23791d88861dc29227ac6a998ad7e3bf8232bb /src/northbridge/intel/haswell/pei_data.h
parentd92d7cb515aa1222d2b8e500157d4b911d7c8783 (diff)
xeon_sp/cpx: Update meminfo max_capacity_mib and number_of_devices
The values can be used during SMBIOS type 16 creation. Tested=On OCP Delta Lake, dmidecode -t 16 to verify. Handle 0x000A, DMI type 16, 23 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: Single-bit ECC Maximum Capacity: 1146 GB Error Information Handle: Not Provided Number Of Devices: 6 Change-Id: Id8f92dc96a7a3eb2e6db330adda98a7fe6d516c8 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/haswell/pei_data.h')
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