diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-01-15 00:49:03 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-15 12:54:00 +0000 |
| commit | 1db5bc7dac2bb592708f26dede339ffdf3246567 (patch) | |
| tree | d8636a114ebd6ef6830a016de15c92b21f0b740d /src/northbridge/intel/haswell/pei_data.h | |
| parent | 3663d55a23fb64ea88dd1fd18ae4b0ce29e71a61 (diff) | |
nb/intel/haswell: Tidy up code and comments
- Reformat some lines of code
- Put names to all used MCHBAR registers
- Move MCHBAR registers into a separate file, for future expansion
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
Tested, it does not change the binary of Asrock B85M Pro4.
Change-Id: I926289304acb834f9b13cd7902801798f8ee478a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38434
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/pei_data.h')
| -rw-r--r-- | src/northbridge/intel/haswell/pei_data.h | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index dfc34d8ce9..6e537403b3 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -101,10 +101,7 @@ struct pei_data /* Data from MRC that should be saved to flash */ unsigned char *mrc_output; unsigned int mrc_output_len; - /* - * Max frequency DDR3 could be ran at. Could be one of four values: 800, - * 1067, 1333, 1600 - */ + /* Max frequency to run DDR3 at. Can be one of four values: 800, 1067, 1333, 1600 */ uint32_t max_ddr3_freq; /* Route all USB ports to XHCI controller in resume path */ int usb_xhci_on_resume; |