From 1db5bc7dac2bb592708f26dede339ffdf3246567 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 15 Jan 2020 00:49:03 +0100 Subject: nb/intel/haswell: Tidy up code and comments - Reformat some lines of code - Put names to all used MCHBAR registers - Move MCHBAR registers into a separate file, for future expansion - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0) Tested, it does not change the binary of Asrock B85M Pro4. Change-Id: I926289304acb834f9b13cd7902801798f8ee478a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/38434 Reviewed-by: David Hendricks Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/pei_data.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'src/northbridge/intel/haswell/pei_data.h') diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index dfc34d8ce9..6e537403b3 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -101,10 +101,7 @@ struct pei_data /* Data from MRC that should be saved to flash */ unsigned char *mrc_output; unsigned int mrc_output_len; - /* - * Max frequency DDR3 could be ran at. Could be one of four values: 800, - * 1067, 1333, 1600 - */ + /* Max frequency to run DDR3 at. Can be one of four values: 800, 1067, 1333, 1600 */ uint32_t max_ddr3_freq; /* Route all USB ports to XHCI controller in resume path */ int usb_xhci_on_resume; -- cgit v1.2.3