diff options
author | Jakub Czapiga <jacz@semihalf.com> | 2022-02-15 11:50:31 +0100 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-08 16:06:33 +0000 |
commit | ad6157ebdfddc39b95e388487e00cadd2bbf368b (patch) | |
tree | bbb85c9b13faf74515387ee8978eefd6d79e6b06 /src/northbridge/intel/haswell/haswell_mrc | |
parent | e96ade6981c60af4d6f24471d7f6a440ab7bfd4e (diff) |
timestamps: Rename timestamps to make names more consistent
This patch aims to make timestamps more consistent in naming,
to follow one pattern. Until now there were many naming patterns:
- TS_START_*/TS_END_*
- TS_BEFORE_*/TS_AFTER_*
- TS_*_START/TS_*_END
This change also aims to indicate, that these timestamps can be used
to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/northbridge/intel/haswell/haswell_mrc')
-rw-r--r-- | src/northbridge/intel/haswell/haswell_mrc/raminit.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index e1a933766a..5336769404 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -405,13 +405,13 @@ void perform_raminit(const int s3resume) pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0); pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1); - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); copy_spd(&pei_data, &spdi); sdram_initialize(&pei_data); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); post_code(0x3b); |