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authorAngel Pons <th3fanbus@gmail.com>2021-01-20 15:03:30 +0100
committerAngel Pons <th3fanbus@gmail.com>2021-01-30 23:11:15 +0000
commit32770f840d768b46d123893ecb87bb9095e4655d (patch)
treea7be1d28d56411a76d28e6b304e02b5b482fb033 /src/northbridge/intel/haswell/haswell.h
parent9debbd65af390cb86b89457943e7ea57c8c3f8a8 (diff)
nb/intel/haswell: Define and use MMCONF_BUS_NUMBER
Change-Id: I0d6338f763a78895b1ae14d1ab68253851b6c283 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49763 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/haswell.h')
-rw-r--r--src/northbridge/intel/haswell/haswell.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index d28c7d4fc0..f6678cab2d 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -92,8 +92,6 @@ void haswell_unhide_peg(void);
void report_platform_info(void);
-int decode_pcie_bar(u32 *const base, u32 *const len);
-
#include <device/device.h>
struct acpi_rsdp;