diff options
| author | Keith Hui <buurin@gmail.com> | 2023-11-11 17:25:48 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-26 11:08:14 +0000 |
| commit | b4f47e8067a7ef55ad5e2f18058031a871edbfef (patch) | |
| tree | 1a6046ce808e6a03070a66efcf125cbc74b8cb17 /src/northbridge/intel/haswell/chip.h | |
| parent | e9ed7928cf31312629b30acd6a1788a64f547baf (diff) | |
nb/intel/haswell: Move SPD addresses to devicetree
Introduce a sandybridge-style devicetree setting for SPD addresses,
and use it instead of runtime code in mb_get_spd_map() for all
haswell boards without CONFIG(HAVE_SPD_IN_CBFS) - effectively all
boards except google/slippy.
Patch also covers recently added Z97 boards using Broadwell MRC.
Also update util/autoport to match.
abuild passes for all affected boards.
autoport builds, but otherwise untested.
Change-Id: I574aec9cb6a47c8aaf275ae06c7e1fb695534b34
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79025
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/chip.h')
| -rw-r--r-- | src/northbridge/intel/haswell/chip.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 274e549e2d..dc71340bd6 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -39,6 +39,8 @@ struct northbridge_intel_haswell_config { bool usb_xhci_on_resume; struct i915_gpu_controller_info gfx; + + u8 spd_addresses[4]; }; #endif /* NORTHBRIDGE_INTEL_HASWELL_CHIP_H */ |