diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2024-05-12 11:50:08 +0200 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2024-05-13 17:12:45 +0000 |
| commit | ca3764ab18efdc7921689c6de1dc4adcddf07207 (patch) | |
| tree | fa852d45dfc6e97977bb1318cadab52acd6506e7 /src/northbridge/intel/haswell/broadwell_mrc | |
| parent | 200075ba2dc5697a09e9dcd6b41390e7435a5ed5 (diff) | |
nb/intel/haswell: Use <device/dram/ddr3.h>
Change-Id: I353ceb7ab5ec0c82f5e717c856ad7934fcbd03b6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82355
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/broadwell_mrc')
| -rw-r--r-- | src/northbridge/intel/haswell/broadwell_mrc/raminit.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c index 7af21f578a..0bb6f28a6a 100644 --- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c @@ -8,6 +8,7 @@ #include <cbmem.h> #include <cbfs.h> #include <cf9_reset.h> +#include <device/dram/ddr3.h> #include <memory_info.h> #include <mrc_cache.h> #include <device/device.h> @@ -245,7 +246,6 @@ static void setup_sdram_meminfo(struct pei_data *pei_data) } #include <device/smbus_host.h> -#define SPD_LEN 256 /* Copy SPD data for on-board memory */ static void copy_spd(struct pei_data *pei_data, struct spd_info *spdi) @@ -261,20 +261,21 @@ static void copy_spd(struct pei_data *pei_data, struct spd_info *spdi) if (!spd_file) die("SPD data not found."); - if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) { + if (spd_file_len < ((spdi->spd_index + 1) * SPD_SIZE_MAX_DDR3)) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); spdi->spd_index = 0; } - if (spd_file_len < SPD_LEN) + if (spd_file_len < SPD_SIZE_MAX_DDR3) die("Missing SPD data."); /* MRC only uses index 0, but coreboot uses the other indices */ - memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_LEN), SPD_LEN); + memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_SIZE_MAX_DDR3), + SPD_SIZE_MAX_DDR3); for (size_t i = 1; i < ARRAY_SIZE(spdi->addresses); i++) { if (spdi->addresses[i] == SPD_MEMORY_DOWN) - memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_LEN); + memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_SIZE_MAX_DDR3); } } |