diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-01-21 21:05:54 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-26 22:40:53 +0000 |
| commit | e98722856e37c31152f1561891a1428a7bdbb557 (patch) | |
| tree | 30bd6574ccadbf31d0ff801f663288d6d99b3683 /src/northbridge/intel/gm45 | |
| parent | 92b487dd4b842b5bb614d4e525b0f32bde1d8ca1 (diff) | |
soc/intel/cannonlake: Add Cannonlake D0 support in mpinit and report
Both early platform information reporting in bootblock and common code
CPU driver will add support for cannonlake D0 stepping processor.
BUG=None
TEST=Boot up system with D0 stepping CPU installed, check serial log
that can display as D0 stepping.
Change-Id: I76ee974ee027100d7853a110f95b1601987492e4
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/gm45')
0 files changed, 0 insertions, 0 deletions