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authorElyes HAOUAS <ehaouas@noos.fr>2019-03-04 17:49:46 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-03-06 20:03:55 +0000
commit89989cf61f93fdbb0b61474d16fbc0dfdf419944 (patch)
tree898f5542ee0abc00102d78e940e7668d74fbf75e /src/northbridge/intel/gm45
parentc2209e4befd047e76ef281bedd6a5e859f6ba65c (diff)
src: Drop unused include <arch/acpi.h>
Change-Id: I1f44ffeb54955ed660162a791c6281f292b1116a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/northbridge/intel/gm45')
-rw-r--r--src/northbridge/intel/gm45/iommu.c1
-rw-r--r--src/northbridge/intel/gm45/northbridge.c1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c
index 93e631638e..b6e38e7e72 100644
--- a/src/northbridge/intel/gm45/iommu.c
+++ b/src/northbridge/intel/gm45/iommu.c
@@ -19,7 +19,6 @@
#include <device/pci_ops.h>
#include <device/pci_def.h>
-#include <arch/acpi.h>
#include "gm45.h"
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index eda5e92225..40e4f61afd 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -27,7 +27,6 @@
#include <cpu/intel/smm/gen1/smi.h>
#include "chip.h"
#include "gm45.h"
-#include "arch/acpi.h"
/* Reserve segments A and B:
*