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authorElyes Haouas <ehaouas@noos.fr>2024-05-06 11:48:41 +0200
committerElyes Haouas <ehaouas@noos.fr>2024-05-07 10:53:31 +0000
commit8bcd8210ea64bdbb35485d361e645f2c9cfcf763 (patch)
tree7f36324e0d9e90e03f239974c7ae99220616c6d7 /src/northbridge/intel/gm45
parent0f45e17f564a657ddf9804124e4e30da0edb1d13 (diff)
dram/ddr3: Use the same naming convention as DDR4
Change-Id: Ifaff19c0117b5247d3321605ccc2e97bf8226ca8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82216 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45')
-rw-r--r--src/northbridge/intel/gm45/raminit_meminfo.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/intel/gm45/raminit_meminfo.c b/src/northbridge/intel/gm45/raminit_meminfo.c
index c2c7f510d8..9fd4065ffc 100644
--- a/src/northbridge/intel/gm45/raminit_meminfo.c
+++ b/src/northbridge/intel/gm45/raminit_meminfo.c
@@ -24,14 +24,14 @@ static u8 get_dimm_mod_type(const sysinfo_t *sysinfo, const int idx)
static void ddr3_read_ids(const sysinfo_t *sysinfo, struct dimm_info *dimm, const int idx)
{
const u8 addr = sysinfo->spd_map[idx];
- for (int k = 0; k < SPD_DIMM_SERIAL_LEN; k++) {
- dimm->serial[k] = smbus_read_byte(addr, SPD_DIMM_SERIAL_NUM + k);
+ for (int k = 0; k < SPD_DDR3_SERIAL_LEN; k++) {
+ dimm->serial[k] = smbus_read_byte(addr, SPD_DDR3_SERIAL_NUM + k);
}
- for (int k = 0; k < SPD_DIMM_PART_LEN; k++) {
- dimm->module_part_number[k] = smbus_read_byte(addr, SPD_DIMM_PART_NUM + k);
+ for (int k = 0; k < SPD_DDR3_PART_LEN; k++) {
+ dimm->module_part_number[k] = smbus_read_byte(addr, SPD_DDR3_PART_NUM + k);
}
- dimm->mod_id = (smbus_read_byte(addr, SPD_DIMM_MOD_ID2) << 8) |
- (smbus_read_byte(addr, SPD_DIMM_MOD_ID1) << 0);
+ dimm->mod_id = (smbus_read_byte(addr, SPD_DDR3_MOD_ID2) << 8) |
+ (smbus_read_byte(addr, SPD_DDR3_MOD_ID1) << 0);
}
static u32 get_mem_clock_mt(const int clock_index)