diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-12 14:35:25 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-28 11:59:17 +0000 |
commit | be9533aba957e9c43f77381f436906951c13c98b (patch) | |
tree | b4ad42a54424f29043ce91b7d5135e6de2cad6f1 /src/northbridge/intel/gm45/romstage.c | |
parent | 942ad6a137027d6a7d8d082dee20bb64c81dc813 (diff) |
nb/intel/gm45: Add C_ENVIRONMENT_BOOTBLOCK support
The i82801ix_early_init is now called both in the bootblock and
romstage. The rationale behind setting this up twice is to ensure
bootblock-romstage compatibility in the future if for instance VBOOT
is used.
This moves the console init to the bootblock.
The romstage now runs uncached. Adding a prog_run hooks to set up an
MTRR to cache the romstage will be done in a followup patch.
The default size of 64KiB is not modified for the bootblock as trying
to fit both EHCI and SPI flash debugging needs a more space and 64KiB
is the next power of 2 size that fits it.
TESTED on Thinkpad X200.
Change-Id: I8f59736cb54377973215f35e35d2cbcd1d82c374
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/gm45/romstage.c')
-rw-r--r-- | src/northbridge/intel/gm45/romstage.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index 7f45ca7f83..a146734158 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -62,12 +62,6 @@ void mainboard_romstage_entry(void) i82801ix_early_init(); setup_pch_gpios(&mainboard_gpio_map); - i82801ix_lpc_decode(); - - mb_setup_superio(); - - console_init(); - reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) { |