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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-06-30 21:00:07 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-04 06:52:07 +0000 |
commit | 8f23b5d4343c5c8ec1f7f7d453f9d8784fc0d5a2 (patch) | |
tree | 16f6a9887c64ae65376692e79d03cc668a5a2ca1 /src/northbridge/intel/gm45/ram_calc.c | |
parent | 2874330828fa6950bccba04872dbfc8cfae91d99 (diff) |
drivers/intel/fsp1_1: Adjust postcar MTRRs
Use of romstage_ram_stack_bottom() was invalid, it
potentially uses a different ROMSTAGE_RAM_STACK_SIZE
from the postcar_frame_init() call.
If alignment evaluated to 1 MiB, that WB MTRR may not
have covered all of CBMEM range, having some impact
on boot speeds.
There is no need to accurately describe write-back
MTRR ranges for postcar.
Change-Id: Icb65cef079df56fadcc292c648cab8bdbb667f47
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/gm45/ram_calc.c')
0 files changed, 0 insertions, 0 deletions