diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-24 23:25:13 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-28 06:49:19 +0000 |
| commit | 8b76605a4af9b45894c39cd7b9c480bd96f523cd (patch) | |
| tree | 4d24a5aa80b7e6e1b19ef62868fc442aa1a8c128 /src/northbridge/intel/gm45/ram_calc.c | |
| parent | a050817ce57ef960bf2bec3a18f23b59039dd184 (diff) | |
nb/intel/gm45: Allocate a 8M TSEG region
Tested on Thinkpad X200.
Change-Id: I9db7a71608aaec956a7b22649498b97d58f35265
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23418
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45/ram_calc.c')
| -rw-r--r-- | src/northbridge/intel/gm45/ram_calc.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 780bed48b1..1e434c7689 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -65,6 +65,24 @@ u32 decode_igd_gtt_size(const u32 gsm) } } +/* Decodes TSEG region size to kilobytes. */ +u32 decode_tseg_size(u8 esmramc) +{ + if (!(esmramc & 1)) + return 0; + switch ((esmramc >> 1) & 3) { + case 0: + return 1 << 10; + case 1: + return 2 << 10; + case 2: + return 8 << 10; + case 3: + default: + die("Bad TSEG setting.\n"); + } +} + static uintptr_t smm_region_start(void) { const pci_devfn_t dev = PCI_DEV(0, 0, 0); @@ -76,12 +94,15 @@ static uintptr_t smm_region_start(void) /* Graphics memory comes next */ const u32 ggc = pci_read_config16(dev, D0F0_GGC); + const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC); if (!(ggc & 2)) { /* Graphics memory */ tor -= decode_igd_memory_size((ggc >> 4) & 0xf) << 10; /* GTT Graphics Stolen Memory Size (GGMS) */ tor -= decode_igd_gtt_size((ggc >> 8) & 0xf) << 10; } + /* TSEG size */ + tor -= decode_tseg_size(esmramc) << 10; return tor; } |