diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-08-19 21:41:06 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-21 16:32:10 +0000 |
| commit | dddd1cc6913bd0cbb814b68de7315cb84bfb9c2f (patch) | |
| tree | e4ad63b1db7fbeaf14ad5bf60046a0ed063b86a5 /src/northbridge/intel/gm45/gm45.h | |
| parent | 7aa3372ce21565962d4cb1090e1f194b6f33f968 (diff) | |
src/northbridge: Drop unneeded empty lines
Change-Id: I5f3118f0f855160ed49adc543b6169fccd7520ee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44593
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45/gm45.h')
| -rw-r--r-- | src/northbridge/intel/gm45/gm45.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index d18b3d42c8..dc993cfb3c 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -170,7 +170,6 @@ enum { #define CMOS_WRITE_TRAINING 0x90 /* 16 bytes (could be reduced to 10 bytes) */ - #ifndef __ACPI__ #define DEFAULT_MCHBAR ((u8 *)0xfed14000) #define DEFAULT_DMIBAR ((u8 *)0xfed18000) @@ -181,7 +180,6 @@ enum { #define DEFAULT_EPBAR 0xfed19000 #define DEFAULT_HECIBAR ((u8 *)0xfed1a000) - #define IOMMU_BASE1 0xfed90000 #define IOMMU_BASE2 0xfed91000 #define IOMMU_BASE3 0xfed92000 @@ -358,7 +356,6 @@ enum { #define CxDTAEW(x) (0x1280+(x*0x100)) #define CxDTC(x) (0x1288+(x*0x100)) - /* * DMIBAR */ @@ -376,7 +373,6 @@ enum { #define DMILE2D 0x60 #define DMILE2A 0x68 - /* * EPBAR */ @@ -390,7 +386,6 @@ enum { #define EPLE1A 0x58 #define EPLE2D 0x60 - #ifndef __ACPI__ void gm45_early_init(void); void gm45_early_reset(void); |