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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-05 21:46:53 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-07 17:48:48 +0000 |
| commit | 5a7e4a59821905350c1cdfc3ddbf571c041d800e (patch) | |
| tree | dea8e677120eacc9fa89d5fc44b902b4f61ff579 /src/northbridge/intel/gm45/chip.h | |
| parent | b726e091575aa979e3a57565692bfb8dc53b0915 (diff) | |
soc/amd/cezanne/chip: add PCI bus scanning
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I76b0eb4470ac4a48e1caeaf507b5e6c45bb88119
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/gm45/chip.h')
0 files changed, 0 insertions, 0 deletions