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authorSubrata Banik <subratabanik@google.com>2024-06-27 15:47:36 +0530
committerSubrata Banik <subratabanik@google.com>2024-07-03 06:12:55 +0000
commit727bc0803722abda1dc1229ac9c7dc4405b5a5c4 (patch)
tree82df27e54da2bc7847737b394dbd9edea6a0ce01 /src/northbridge/intel/gm45/Makefile.mk
parentd05fe9fd3ce9c741ff802a32229c85ab14420702 (diff)
soc/intel/cmn/cse: Modify dependency on CSE lite configs
Refactor CSE lite configs (specifically CSE sync related) to support the alternative of sending CSE communication from the payload. When the SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD config is selected, coreboot will skip initiating CSE sync operations and rely on the payload CSE driver implementation. The following configs are modified to ensure coreboot skips CSE communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled: - SOC_INTEL_CSE_LITE_PSR - SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY - SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE - SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I5ddaf6e29949231db84b14bf7ea2d34866bb8e6c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83228 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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