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authorArthur Heymans <arthur@aheymans.xyz>2018-06-03 12:42:10 +0200
committerArthur Heymans <arthur@aheymans.xyz>2018-06-05 07:49:30 +0000
commit3a4edb6ea815fa24f02daeae9b80e6bde0871a9e (patch)
tree9b2ca36db034e16f22edf101dbcd2d5ea3acfb3a /src/northbridge/intel/gm45/Makefile.inc
parent4ff675ebd071755dcb278836a16ae1ea10c63e50 (diff)
nb/intel/gm45: Switch to POSTCAR_STAGE
Change-Id: I02165cf63710bedcafe9287cbe8a1d1fe41ebae2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26788 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45/Makefile.inc')
-rw-r--r--src/northbridge/intel/gm45/Makefile.inc2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc
index fdf0012ec4..c12bbf14ae 100644
--- a/src/northbridge/intel/gm45/Makefile.inc
+++ b/src/northbridge/intel/gm45/Makefile.inc
@@ -36,4 +36,6 @@ ramstage-y += gma.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c
+postcar-y += ram_calc.c
+
endif