northbridge/intel/fsp_*: Remove legacy SoCs

* Remove FSP Sandy/Ivybrige which are unused.
* Open Source implementation isn't final but
  good enough to replace FSP version.
* For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE
  and NORTHBRIDGE_INTEL_SANDYBRIDGE

Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/29402
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 34 deletions

diff --git a/src/northbridge/intel/fsp_sandybridge/ram_calc.c b/src/northbridge/intel/fsp_sandybridge/ram_calc.c
deleted file mode 100644
index f51de6d27a..0000000000
--- a/src/northbridge/intel/fsp_sandybridge/ram_calc.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define __SIMPLE_DEVICE__
-
-#include <arch/io.h>
-#include <cbmem.h>
-#include <fsp_util.h>
-#include "northbridge.h"
-
-static uintptr_t smm_region_start(void)
-{
-	/* Base of TSEG is top of usable DRAM */
-	uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG) & ~(1UL << 0);
-	return tom;
-}
-
-void *cbmem_top(void)
-{
-	return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE);
-}