Remove sandybridge and ivybridge FSP code path

We already have two other code paths for this silicon. Maintaining the
FSP path as well doesn't make much sense. There was only one board to
use this code, and it's a reference board that I doubt anyone still
owns or uses.

Change-Id: I4fcfa6c56448416624fd26418df19b354eb72f39
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11789
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>

1 files changed, 0 insertions, 45 deletions

diff --git a/src/northbridge/intel/fsp_sandybridge/chip.h b/src/northbridge/intel/fsp_sandybridge/chip.h
deleted file mode 100644
index 6e823dc986..0000000000
--- a/src/northbridge/intel/fsp_sandybridge/chip.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <drivers/intel/gma/i915.h>
-
-/*
- * Digital Port Hotplug Enable:
- *  0x04 = Enabled, 2ms short pulse
- *  0x05 = Enabled, 4.5ms short pulse
- *  0x06 = Enabled, 6ms short pulse
- *  0x07 = Enabled, 100ms short pulse
- */
-struct northbridge_intel_fsp_sandybridge_config {
-	u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */
-	u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
-	u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
-
-	u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */
-	u8 gpu_panel_power_cycle_delay;          /* T4 time sequence */
-	u16 gpu_panel_power_up_delay;            /* T1+T2 time sequence */
-	u16 gpu_panel_power_down_delay;          /* T3 time sequence */
-	u16 gpu_panel_power_backlight_on_delay;  /* T5 time sequence */
-	u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
-
-	u32 gpu_cpu_backlight;	/* CPU Backlight PWM value */
-	u32 gpu_pch_backlight;	/* PCH Backlight PWM value */
-
-	struct i915_gpu_controller_info gfx;
-};