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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-20 19:20:16 +0200 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-06 09:41:43 +0100 |
commit | 8e73821ce2603fd1b16cf32797904ddf2f2d9828 (patch) | |
tree | a2b3ce6b86ac81b14c5e2c9575a81b8f9cc6c8d7 /src/northbridge/intel/fsp_sandybridge/bootblock.c | |
parent | 6220eec18816f816cae28c07c6afcaf1673d83c6 (diff) |
intel/fsp_sandybridge: Switch to MMCONF_SUPPORT_DEFAULT
Untested.
Change-Id: I61ab1e5279c995f933971332673aa4ca0150e80c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17544
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/fsp_sandybridge/bootblock.c')
-rw-r--r-- | src/northbridge/intel/fsp_sandybridge/bootblock.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/bootblock.c b/src/northbridge/intel/fsp_sandybridge/bootblock.c new file mode 100644 index 0000000000..1c1d49214b --- /dev/null +++ b/src/northbridge/intel/fsp_sandybridge/bootblock.c @@ -0,0 +1,26 @@ +#include <arch/io.h> + +/* Just re-define this instead of including sandybridge.h. It blows up romcc. */ +#define PCIEXBAR 0x60 + +static void bootblock_northbridge_init(void) +{ + uint32_t reg; + + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = 0; + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg); + reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); +} |