Add Intel FSP northbridge support Sandybridge and Ivybridge

Add support for Sandybridge and Ivybridge using the Intel FSP.
The FSP is different enough to warrant its own source files.
This source handle the majority of FSP interaction.

"Intel® Firmware Support Package (Intel® FSP) provides key
programming information for initializing Intel® silicon and can be
easily integrated into a boot loader of the developer’s choice.
It is easy to adopt, scalable to design, reduces time-to-market, and
is economical to build."
http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html

Change-Id: Ib879c6b0fbf2eb1cbf929a87f592df29ac48bcc5
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4015
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 122 insertions, 0 deletions

diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig
new file mode 100644
index 0000000000..0c3d5f5156
--- /dev/null
+++ b/src/northbridge/intel/fsp_sandybridge/Kconfig
@@ -0,0 +1,122 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Google Inc.
+## Copyright (C) 2013 Sage Electronic Engineering, LLC.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE
+	bool
+	select CPU_INTEL_FSP_MODEL_206AX
+
+config NORTHBRIDGE_INTEL_FSP_IVYBRIDGE
+	bool
+	select CPU_INTEL_FSP_MODEL_306AX
+
+if NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE
+
+config HAVE_FSP_BIN
+	bool "Use Intel Firmware Support Package"
+	help
+	  Select this option to add an Intel FSP binary to
+	  the resulting coreboot image.
+
+	  Note: Without this binary, coreboot builds relying on the FSP
+	  will not boot
+
+config VGA_BIOS_ID
+	string
+	default "8086,0106"
+	help
+	  This is the default PCI ID for the sandybridge/ivybridge graphics
+	  devices.  This string names the vbios rom in cbfs.  The following
+	  PCI IDs will be remapped to load this rom:
+	  0x80860102, 0x8086010a, 0x80860112, 0x80860116
+	  0x80860122, 0x80860126, 0x80860166
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xff7f0000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x10000
+
+
+if HAVE_FSP_BIN
+
+config FSP_FILE
+	string "Intel FSP binary path and filename"
+	default "../intel/fsp/ivybridge_bd82x6x/FvFsp.bin" if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X
+	default "../intel/fsp/ivybridge_i89xx/FvFsp.bin" if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_I89XX
+	help
+	  The path and filename of the Intel FSP binary for this platform.
+
+config FSP_LOC
+	hex "Intel FSP Binary location in cbfs"
+	default 0xfff80000
+	help
+	  The location in cbfs that the FSP is located. This must match the
+	  value that is set in the FSP binary.  If the FSP needs to be moved,
+	  rebase the FSP with the Intel's BCT (tool).
+
+config CBFS_SIZE
+	hex "Size of CBFS filesystem in ROM"
+	default 0x100000
+	help
+	  On Sandybridge and Ivybridge systems the firmware image may
+	  have to store a lot more than just coreboot, including:
+	   - a firmware descriptor
+	   - Intel Management Engine firmware
+	  This option specifies the maximum size of the CBFS portion in the
+	  firmware image.
+
+config ENABLE_FAST_BOOT
+	bool "Enable Fast Boot"
+	default y if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X
+	depends on !CACHE_ROM
+	help
+	  Enabling this feature will cause MRC data to be cached in NV storage
+	  which will speed up boot time on future reboots and/or power cycles.
+
+	  WARNING: This feature combined with the CACHE_ROM may result in undefined
+	  behavior.
+
+config MRC_CACHE_SIZE
+	hex "MRC Data Cache Size"
+	default 0x10000
+	depends on ENABLE_FAST_BOOT
+	help
+	  This is the amount of space in NV storage that is reserved for MRC data
+	  cache storage when using fast boot.
+
+config VIRTUAL_ROM_SIZE
+	hex "Virtual ROM Size"
+	default ROM_SIZE
+	depends on ENABLE_FAST_BOOT
+	help
+	  This is used to calculate the offset of the MRC data cache in NV
+	  Storage for "Fast Boot".  If in doubt, leave this set to the default
+	  which sets the virtual size equal to the ROM size.
+
+	  Example: Cougar Canyon 2 has 2 8 MB SPI ROMs.  When the SPI ROMs are
+	  loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB.  When
+	  the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
+	  size is 16 MB.
+
+endif # HAVE_FSP_BIN
+
+endif # NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE