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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-12-22 12:28:07 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-01-27 22:48:06 +0100
commitf1e3c763b3eef15dbfae73f485408a0dec230d00 (patch)
tree28682b0d4ad36063b3612c8a774af868a3e55878 /src/northbridge/intel/fsp_rangeley
parent91fac61240612291f7be3362f7acad31803e8b03 (diff)
CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM
The name was always obscure and confusing. Instead define cbmem_top() directly in the chipset code for x86 like on ARMs. TODO: Check TSEG alignment, it used for MTRR programming. Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7888 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/northbridge/intel/fsp_rangeley')
-rw-r--r--src/northbridge/intel/fsp_rangeley/raminit.c14
1 files changed, 9 insertions, 5 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/raminit.c
index 3513c0f33d..9626745e47 100644
--- a/src/northbridge/intel/fsp_rangeley/raminit.c
+++ b/src/northbridge/intel/fsp_rangeley/raminit.c
@@ -26,19 +26,23 @@
#include "northbridge.h"
#include <drivers/intel/fsp/fsp_util.h>
-unsigned long get_top_of_ram(void)
+static uintptr_t smm_region_start(void)
{
/*
* Calculate the top of usable (low) DRAM.
* The FSP's reserved memory sits just below the SMM region,
* allowing calculation of the top of usable memory.
*/
- u32 tom = sideband_read(B_UNIT, BMBOUND);
- u32 bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20;
+ uintptr_t tom = sideband_read(B_UNIT, BMBOUND);
+ uintptr_t bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20;
if (bsmmrrl) {
tom = bsmmrrl;
}
- tom -= FSP_RESERVE_MEMORY_SIZE;
- return (unsigned long) tom;
+ return tom;
+}
+
+void *cbmem_top(void)
+{
+ return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE);
}