diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2017-05-31 18:21:59 +0200 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2017-06-08 11:40:59 +0200 |
| commit | 6ab7e5e0906b02b29e9634343f3e9ca722a1088e (patch) | |
| tree | 0850503baa97f2531122103eaa8dd747c6e82534 /src/northbridge/intel/fsp_rangeley/udelay.c | |
| parent | a038835716b3a09bd3d5ab3fd7e3d48d3c3a6f13 (diff) | |
nb/intel/sandybridge/raminit: Advertise correct frequency
As of Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c the
reference clock can be 100Mhz.
Decode the register and use the reference clock to calculate
the selected DDR frequency.
Tested on Lenovo T430.
Change-Id: I8481564fe96af29ac31482a7f03bb88f343326f4
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/fsp_rangeley/udelay.c')
0 files changed, 0 insertions, 0 deletions