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authorDuncan Laurie <dlaurie@chromium.org>2012-05-25 10:04:17 -0700
committerRonald G. Minnich <rminnich@gmail.com>2012-07-24 00:02:55 +0200
commitda83a5f18e252e4b8e6259fd7c91e67ca25ee6cd (patch)
tree043595fa54f93722ccc415870e3b685e7498db2a /src/northbridge/intel/e7520
parentac2ec34fd28dad54269774b3881bc7aebfb40229 (diff)
Fixes to enable RC6 on IvyBridge
- The unneeded poll on non-MT force-wake bit was timing out and causing the gma_pm_init_pre_vbios() function to exit early so it was not preparing PM registers properly. I changed the gtt_poll() calls to not return on timeout unless it can't proceed so we don't see half-initialized registers. - RC6+ (Deep Render Standby) is not working reliably so we can just enable RC6 in the BIOS and let the kernel decide if it wants to enable RC6+ later. This Kernel message is new in kernel 3.4: [drm] Enabling RC6 states: RC6 on, RC6p off, RC6pp off Change-Id: I69d005ba56be8c7684a4ea1133a1d761f7c07acc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1268 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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