diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-07 11:16:35 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-12 16:03:45 +0000 |
| commit | d1141ab5a49980de0d7da23879ce6ddf238471af (patch) | |
| tree | a9e1347bb6c7066909a53e3ab82dfbb8a99d822e /src/northbridge/intel/e7505/romstage.c | |
| parent | 61af679838ab52318641828b6a77c81229033c77 (diff) | |
intel/e7505,i82801dx: Refactor raminit
Avoid direct enable_smbus() call from northbridge code.
Change-Id: I077e455242db9fc0f86432bd1afab75cb6fb6f4c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/e7505/romstage.c')
| -rw-r--r-- | src/northbridge/intel/e7505/romstage.c | 27 |
1 files changed, 5 insertions, 22 deletions
diff --git a/src/northbridge/intel/e7505/romstage.c b/src/northbridge/intel/e7505/romstage.c index 6c74c1febf..f506bf4894 100644 --- a/src/northbridge/intel/e7505/romstage.c +++ b/src/northbridge/intel/e7505/romstage.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#include <stdint.h> #include <cbmem.h> -#include <console/console.h> #include <arch/romstage.h> #include <southbridge/intel/i82801dx/i82801dx.h> @@ -23,27 +21,12 @@ void mainboard_romstage_entry(void) { - static const struct mem_controller memctrl[] = { - { - .d0 = PCI_DEV(0, 0, 0), - .d0f1 = PCI_DEV(0, 0, 1), - .channel0 = { 0x50, 0x52, 0, 0 }, - .channel1 = { 0x51, 0x53, 0, 0 }, - }, - }; + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i82801dx_early_init(); - /* If this is a warm boot, some initialization can be skipped */ - if (!e7505_mch_is_ready()) { - enable_smbus(); - - /* The real MCH initialisation. */ - e7505_mch_init(memctrl); - - /* Hook for post ECC scrub settings and debug. */ - e7505_mch_done(memctrl); - } - - printk(BIOS_DEBUG, "SDRAM is up.\n"); + sdram_initialize(); cbmem_recovery(0); } |