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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2011-10-31 14:18:33 +0200 |
---|---|---|
committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-10-31 15:34:04 +0100 |
commit | 0a0d5e8b86ccc8562ba9761bdd263ebf2667d3c6 (patch) | |
tree | c3420430b3318499242368b27781118e1d46dbbc /src/northbridge/intel/e7505/northbridge.c | |
parent | 20fc631ad2c483fd2bc12e56f3ca8a1572688fb5 (diff) |
Add support for E7505 northbridge.
Adapted from northbridge/intel/e7501 with only minor changes.
This commit provides minimal patch from e7501 and I prefer any
cosmetic clean-up to be done after initial merge.
Due the incomplete register specifications, it is safer to have
e7505 as a separate directory in case I improve it to support
wider range of memory configurations. I have no e7501 to test with.
Change-Id: Iba3bf9d69ff5e9d9ef3a6ebf8259f048c55d637d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/295
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/e7505/northbridge.c')
-rw-r--r-- | src/northbridge/intel/e7505/northbridge.c | 29 |
1 files changed, 21 insertions, 8 deletions
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index e6e955fb4f..1ea3ce9865 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -8,6 +8,7 @@ #include <string.h> #include <bitops.h> #include "chip.h" +#include "e7505.h" #if CONFIG_WRITE_HIGH_TABLES==1 #include <cbmem.h> @@ -65,17 +66,17 @@ static void pci_domain_set_resources(device_t dev) /* Write the ram configuration registers, * preserving the reserved bits. */ - tolm_r = pci_read_config16(mc_dev, 0xc4); + tolm_r = pci_read_config16(mc_dev, TOLM); tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff); - pci_write_config16(mc_dev, 0xc4, tolm_r); + pci_write_config16(mc_dev, TOLM, tolm_r); - remapbase_r = pci_read_config16(mc_dev, 0xc6); + remapbase_r = pci_read_config16(mc_dev, REMAPBASE); remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00); - pci_write_config16(mc_dev, 0xc6, remapbase_r); + pci_write_config16(mc_dev, REMAPBASE, remapbase_r); - remaplimit_r = pci_read_config16(mc_dev, 0xc8); + remaplimit_r = pci_read_config16(mc_dev, REMAPLIMIT); remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00); - pci_write_config16(mc_dev, 0xc8, remaplimit_r); + pci_write_config16(mc_dev, REMAPLIMIT, remaplimit_r); /* Report the memory regions */ idx = 10; @@ -98,12 +99,23 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } +static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations intel_pci_ops = { + .set_subsystem = intel_set_subsystem, +}; + static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, + .ops_pci = &intel_pci_ops, .ops_pci_bus = &pci_cf8_conf1, }; @@ -135,7 +147,8 @@ static void enable_dev(struct device *dev) } } -struct chip_operations northbridge_intel_e7501_ops = { - CHIP_NAME("Intel E7501 Northbridge") +struct chip_operations northbridge_intel_e7505_ops = { + CHIP_NAME("Intel E7505 Northbridge") .enable_dev = enable_dev, }; + |