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| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2021-03-12 18:28:03 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-17 08:01:14 +0000 |
| commit | 61dd05e010d91447eafff11cd65baab4e21e0bdb (patch) | |
| tree | 0bd58dc3ca3e27bd80e645a6f7a0418d6cde6cb7 /src/northbridge/intel/e7505/Makefile.inc | |
| parent | 4248d8e7bb1934979a2fc1b4479429a068f0441f (diff) | |
soc/intel/alderlake: Enable CSE Lite driver for ADL platform in romstage
This patch sets up cse_fw_sync() call in the romstage. The cse_fw_sync()
must be called after DRAM initialization.
Test=Verified on Alderlake platform
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I6779f4a9e140deebf7f3cecd9fc5dac18813f246
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/northbridge/intel/e7505/Makefile.inc')
0 files changed, 0 insertions, 0 deletions