diff options
| author | Greg Watson <jarrah@users.sourceforge.net> | 2004-06-05 14:36:23 +0000 |
|---|---|---|
| committer | Greg Watson <jarrah@users.sourceforge.net> | 2004-06-05 14:36:23 +0000 |
| commit | 8ce104f487a8248be143b4436b7a4abc3969bb6f (patch) | |
| tree | 25b52793e9be2be4b78a666f29e1d44e45722714 /src/northbridge/ibm/cpc710/cpc710_pci.h | |
| parent | 2f2e63bc7dd27b526d300a7aa712a0af4ec85e3e (diff) | |
memory and pci up!
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/ibm/cpc710/cpc710_pci.h')
| -rw-r--r-- | src/northbridge/ibm/cpc710/cpc710_pci.h | 51 |
1 files changed, 34 insertions, 17 deletions
diff --git a/src/northbridge/ibm/cpc710/cpc710_pci.h b/src/northbridge/ibm/cpc710/cpc710_pci.h index e2e12f21f3..a859ce374f 100644 --- a/src/northbridge/ibm/cpc710/cpc710_pci.h +++ b/src/northbridge/ibm/cpc710/cpc710_pci.h @@ -24,24 +24,41 @@ #ifndef _CPC710_PCI_H_ #define _CPC710_PCI_H_ -#define CPC710_PCI_MEMORY_PHYS 0x00000000 -#define CPC710_PCI_MEMORY_BUS 0x80000000 -#define CPC710_PCI_MEMORY_MAXSIZE 0x20000000 +#define CPC710_PCI32_CONFIG (PCIC0_CFGADDR & 0xfff00000) +#define CPC710_PCI32_MEM_SIZE 0xf8000000 +#define CPC710_PCI32_MEM_BASE 0xc0000000 +#define CPC710_PCI32_IO_SIZE 0xf8000000 +#define CPC710_PCI32_IO_BASE 0x80000000 -#define CPC710_BRIDGE_CPCI_PHYS 0xff500000 -#define CPC710_BRIDGE_CPCI_MEM_SIZE 0x08000000 -#define CPC710_BRIDGE_CPCI_MEM_PHYS 0xf0000000 -#define CPC710_BRIDGE_CPCI_MEM_BUS 0x00000000 -#define CPC710_BRIDGE_CPCI_IO_SIZE 0x02000000 -#define CPC710_BRIDGE_CPCI_IO_PHY 0xfc000000 -#define CPC710_BRIDGE_CPCI_IO_BUS 0x00000000 +//#define CPC710_PCI64_CONFIG 0xff400000 +//#define CPC710_PCI64_MEM_SIZE 0xf8000000 +//#define CPC710_PCI64_MEM_BASE 0xc8000000 +//#define CPC710_PCI64_IO_SIZE 0xf8000000 +//#define CPC710_PCI64_IO_BASE 0x88000000 + +#define CPC710_PCIL0_PSEA 0xf6110 +#define CPC710_PCIL0_PCIDG 0xf6120 +#define CPC710_PCIL0_INTACK 0xf7700 +#define CPC710_PCIL0_PIBAR 0xf7800 +#define CPC710_PCIL0_PMBAR 0xf7810 +#define CPC710_PCIL0_CRR 0xf7ef0 +#define CPC710_PCIL0_PR 0xf7f20 +#define CPC710_PCIL0_ACR 0xf7f30 +#define CPC710_PCIL0_MSIZE 0xf7f40 +#define CPC710_PCIL0_IOSIZE 0xf7f60 +#define CPC710_PCIL0_SMBAR 0xf7f80 +#define CPC710_PCIL0_SIBAR 0xf7fc0 +#define CPC710_PCIL0_CTLRW 0xf7fd0 +#define CPC710_PCIL0_CFGADDR 0xf8000 /* little endian */ +#define CPC710_PCIL0_CFGDATA 0xf8010 /* little endian */ +#define CPC710_PCIL0_PSSIZE 0xf8100 +#define CPC710_PCIL0_BARPS 0xf8120 +#define CPC710_PCIL0_PSBAR 0xf8140 +#define CPC710_PCIL0_BPMDLK 0xf8200 +#define CPC710_PCIL0_TPMDLK 0xf8210 +#define CPC710_PCIL0_BIODLK 0xf8220 +#define CPC710_PCIL0_TIODLK 0xf8230 +#define CPC710_PCIL0_INTSET 0xf8310 -#define CPC710_BRIDGE_LOCAL_PHYS 0xff400000 -#define CPC710_BRIDGE_LOCAL_MEM_SIZE 0x04000000 -#define CPC710_BRIDGE_LOCAL_MEM_PHYS 0xf8000000 -#define CPC710_BRIDGE_LOCAL_MEM_BUS 0x40000000 -#define CPC710_BRIDGE_LOCAL_IO_SIZE 0x01000000 -#define CPC710_BRIDGE_LOCAL_IO_PHYS 0xfe000000 -#define CPC710_BRIDGE_LOCAL_IO_BUS 0x04000000 #endif |