diff options
| author | Li-Ta Lo <ollie@lanl.gov> | 2006-03-13 22:18:39 +0000 |
|---|---|---|
| committer | Li-Ta Lo <ollie@lanl.gov> | 2006-03-13 22:18:39 +0000 |
| commit | a413ecc6cd84c964456f2e76972a8f1379fc9c6f (patch) | |
| tree | c2bbc4b716df59948e68baf91d45694a5c157f45 /src/northbridge/amd | |
| parent | 070a1e02d0b6012283b914338ff64127b1d9ffeb (diff) | |
added early_setup.c
removed some messages
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/gx2/raminit.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index 67f5930496..95ce72a10e 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -18,7 +18,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* 1. Initialize GLMC registers base on SPD values, * Hard coded as XpressROM for now */ - print_debug("sdram_enable step 1\r\n"); + //print_debug("sdram_enable step 1\r\n"); msr = rdmsr(0x20000018); msr.hi = 0x10076013; msr.lo = 0x00003000; @@ -39,13 +39,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) msr = rdmsr(0x2000001a); msr.lo = 0x0101; wrmsr(0x2000001a, msr); - print_debug("sdram_enable step 2\r\n"); + //print_debug("sdram_enable step 2\r\n"); /* 3. release CKE mask to enable CKE */ msr = rdmsr(0x2000001d); msr.lo &= ~(0x03 << 8); wrmsr(0x2000201d, msr); - print_debug("sdram_enable step 3\r\n"); + //print_debug("sdram_enable step 3\r\n"); /* 4. set and clear REF_TST 16 times, more shouldn't hurt * why this is before EMRS and MRS ? */ @@ -56,7 +56,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) msr.lo &= ~(0x01 << 3); wrmsr(0x20000018, msr); } - print_debug("sdram_enable step 4\r\n"); + //print_debug("sdram_enable step 4\r\n"); /* 5. set refresh interval */ msr = rdmsr(0x20000018); @@ -68,7 +68,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) msr.lo &= ~(0x03 << 6); msr.lo |= (0x00 << 6); wrmsr(0x20000018, msr); - print_debug("sdram_enable step 5\r\n"); + //print_debug("sdram_enable step 5\r\n"); /* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */ msr = rdmsr(0x20000018); @@ -76,7 +76,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) wrmsr(0x20000018, msr); msr.lo &= ~((0x01 << 28) | 0x01); wrmsr(0x20000018, msr); - print_debug("sdram_enable step 6\r\n"); + //print_debug("sdram_enable step 6\r\n"); /* 7. Reset DLL, Bit 27 is undocumented in GX datasheet, * it is documented in LX datasheet */ @@ -86,7 +86,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) wrmsr(0x20000018, msr); msr.lo &= ~((0x01 << 27) | 0x01); wrmsr(0x20000018, msr); - print_debug("sdram_enable step 7\r\n"); + //print_debug("sdram_enable step 7\r\n"); /* 8. load Mode Register by set and clear PROG_DRAM */ msr = rdmsr(0x20000018); @@ -94,7 +94,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) wrmsr(0x20000018, msr); msr.lo &= ~0x01; wrmsr(0x20000018, msr); - print_debug("sdram_enable step 8\r\n"); + //print_debug("sdram_enable step 8\r\n"); /* wait 200 SDCLKs */ for (i = 0; i < 200; i++) |