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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-12-05 19:31:01 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-04-13 18:48:18 +0000 |
| commit | 8f86fa0da17a7f5ec981fdf09ebb2c6a3c17b2f6 (patch) | |
| tree | 0b77e983aacb1233bd073cefbe5b63ef1b3fe2b0 /src/northbridge/amd | |
| parent | d76beb812915826e9dee6b7edf44d69faa5569e5 (diff) | |
AMD binaryPI: Declare IOAPIC IDs
There is no longer a relation between MAX_CPUS and IOAPIC IDs,
start the cleanup with new declarations.
Change-Id: I65888550e359e55402d99e8816ece2061cfcccbc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/pi/00730F01/acpi_tables.c | 5 | ||||
| -rw-r--r-- | src/northbridge/amd/pi/00730F01/northbridge.c | 7 | ||||
| -rw-r--r-- | src/northbridge/amd/pi/00730F01/state_machine.c | 5 |
3 files changed, 10 insertions, 7 deletions
diff --git a/src/northbridge/amd/pi/00730F01/acpi_tables.c b/src/northbridge/amd/pi/00730F01/acpi_tables.c index 1cf7e74722..bb510cd72c 100644 --- a/src/northbridge/amd/pi/00730F01/acpi_tables.c +++ b/src/northbridge/amd/pi/00730F01/acpi_tables.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <arch/ioapic.h> #include <northbridge/amd/nb_common.h> +#include <southbridge/amd/pi/hudson/ioapic.h> unsigned long acpi_fill_madt(unsigned long current) { @@ -10,11 +11,11 @@ unsigned long acpi_fill_madt(unsigned long current) current = acpi_create_madt_lapics_with_nmis(current); /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS, + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, FCH_IOAPIC_ID, IO_APIC_ADDR, 0); /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS + 1, + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, GNB_IOAPIC_ID, IO_APIC2_ADDR, 24); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index dab0e72d50..644e2d5e3d 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -23,6 +23,7 @@ #include <northbridge/amd/nb_common.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <southbridge/amd/pi/hudson/pci_devs.h> +#include <southbridge/amd/pi/hudson/ioapic.h> #include <amdblocks/cpu.h> #define MAX_NODE_NUMS MAX_NODES @@ -221,7 +222,7 @@ static void nb_set_resources(struct device *dev) static void northbridge_init(struct device *dev) { - setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS + 1); + setup_ioapic((u8 *)IO_APIC2_ADDR, GNB_IOAPIC_ID); } static unsigned long acpi_fill_hest(acpi_hest_t *hest) @@ -253,7 +254,7 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; - ivhd_ioapic->handle = CONFIG_MAX_CPUS; /* FCH IOAPIC ID */ + ivhd_ioapic->handle = FCH_IOAPIC_ID; ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; current += sizeof(ivrs_ivhd_special_t); @@ -263,7 +264,7 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; ivhd_ioapic->reserved = 0x0000; ivhd_ioapic->dte_setting = 0x00; - ivhd_ioapic->handle = CONFIG_MAX_CPUS + 1; /* GNB IOAPIC ID */ + ivhd_ioapic->handle = GNB_IOAPIC_ID; ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; current += sizeof(ivrs_ivhd_special_t); diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c index ba34dabde9..0693a5d93c 100644 --- a/src/northbridge/amd/pi/00730F01/state_machine.c +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -9,6 +9,7 @@ #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/nb_common.h> +#include <southbridge/amd/pi/hudson/ioapic.h> void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { @@ -64,8 +65,8 @@ void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) * when IOMMU build config is enabled otherwise AGESA will skip * it during IOMMU init and IVRS generation. */ - Late->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1; - Late->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS; + Late->GnbLateConfiguration.GnbIoapicId = GNB_IOAPIC_ID; + Late->GnbLateConfiguration.FchIoapicId = FCH_IOAPIC_ID; } /* Code for creating CDIT requires hop count table. If it is not |