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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-09-10 15:10:22 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-17 16:02:27 +0000 |
| commit | 6ca5b475bf286ee8827edee64df5d14b09d936cd (patch) | |
| tree | 83eedb94a05c9e018e4fd8bcb8a8f582ed7afe3d /src/northbridge/amd | |
| parent | 984d0c6afe09360ca4894c12204d21e77a564ef6 (diff) | |
nb/amd/pi/00730F01: enable ACS and AER for PCIe ports
Enable Access Control Services and Advanced Error Reporting for PCI Express
bridges in order to have PCIe devices in separate IOMMU groups for correct
passthrough.
TEST=run dmesg on Debian Buster on PC Engines apu2 and check whether PCIe
devices have separate groups
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I10a8eff0ba37196692f9db6519e498fe535ecd15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/pi/00730F01/northbridge.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index e5a75e8b80..cf4d78b4a6 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -37,6 +37,8 @@ #include <northbridge/amd/agesa/agesa_helper.h> #define MAX_NODE_NUMS MAX_NODES +#define PCIE_CAP_AER BIT(5) +#define PCIE_CAP_ACS BIT(6) typedef struct dram_base_mask { u32 base; //[47:27] at [28:8] @@ -777,6 +779,35 @@ static void fam16_finalize(void *chip_info) pci_write_config32(dev, 0xF8, 0); pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + /* + * Currently it is impossible to enable ACS with AGESA by setting the + * correct bit for AmdInitMid phase. AGESA code path does not call the + * right function that enables these functionalities. Disabled ACS + * result in multiple PCIe devices to be assigned to the same IOMMU + * group. Without IOMMU group separation the devices cannot be passed + * through independently. + */ + + /* Select GPP link core IO Link Strap Control register 0xB0 */ + pci_write_config32(dev, 0xE0, 0x014000B0); + value = pci_read_config32(dev, 0xE4); + + /* Enable AER (bit 5) and ACS (bit 6 undocumented) */ + value |= PCIE_CAP_AER | PCIE_CAP_ACS; + pci_write_config32(dev, 0xE4, value); + + /* Select GPP link core Wrapper register 0x00 (undocumented) */ + pci_write_config32(dev, 0xE0, 0x01300000); + value = pci_read_config32(dev, 0xE4); + + /* + * Enable ACS capabilities straps including sub-items. From lspci it + * looks like these bits enable: Source Validation and Translation + * Blocking + */ + value |= (BIT(24) | BIT(25) | BIT(26)); + pci_write_config32(dev, 0xE4, value); + /* disable No Snoop */ dev = pcidev_on_root(1, 1); if (dev != NULL) { |