Since some people disapprove of white space cleanups mixed in regular commits

while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

21 files changed, 166 insertions, 166 deletions

diff --git a/src/northbridge/amd/amdfam10/amdfam10_conf.c b/src/northbridge/amd/amdfam10/amdfam10_conf.c
index 567790cede..c5506eaca5 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_conf.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_conf.c
@@ -316,7 +316,7 @@ static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes)
 
 	return carry_over;
 }
-#endif 
+#endif
 #endif // CONFIG_AMDMCT
 
 
diff --git a/src/northbridge/amd/amdk8/amdk8_f.h b/src/northbridge/amd/amdk8/amdk8_f.h
index 580f27831b..283e32e235 100644
--- a/src/northbridge/amd/amdk8/amdk8_f.h
+++ b/src/northbridge/amd/amdk8/amdk8_f.h
@@ -87,7 +87,7 @@
 #define DRAM_TIMING_LOW	   0x88
 #define	 DTL_TCL_SHIFT	   0
 #define	 DTL_TCL_MASK	   7
-#define	  DTL_TCL_BASE 	   1 
+#define	  DTL_TCL_BASE 	   1
 #define	  DTL_TCL_MIN	   3
 #define	  DTL_TCL_MAX	   6
 #define	 DTL_TRCD_SHIFT	   4
@@ -125,7 +125,7 @@
 #define   DTL_TRRD_BASE    2
 #define   DTL_TRRD_MIN	   2
 #define   DTL_TRRD_MAX     5
-#define  DTL_MemClkDis_SHIFT 24    /* Channel A */ 
+#define  DTL_MemClkDis_SHIFT 24    /* Channel A */
 #define  DTL_MemClkDis3       (1 << 26)
 #define  DTL_MemClkDis2       (1 << 27)
 #define  DTL_MemClkDis1       (1 << 28)
@@ -135,16 +135,16 @@
 #define  DTL_MemClkDis0_S1g1      (0xa2 << 24)
 
 /* DTL_MemClkDis for m2 and s1g1 is different */
- 
+
 #define DRAM_TIMING_HIGH   0x8c
 #define  DTH_TRWTTO_SHIFT  4
 #define  DTH_TRWTTO_MASK   7
-#define   DTH_TRWTTO_BASE   2 
+#define   DTH_TRWTTO_BASE   2
 #define   DTH_TRWTTO_MIN    2
 #define   DTH_TRWTTO_MAX    9
 #define	 DTH_TWTR_SHIFT	   8
 #define	 DTH_TWTR_MASK	   3
-#define	  DTH_TWTR_BASE	   0 
+#define	  DTH_TWTR_BASE	   0
 #define	  DTH_TWTR_MIN	   1
 #define	  DTH_TWTR_MAX	   3
 #define	 DTH_TWRRD_SHIFT   10
@@ -154,7 +154,7 @@
 #define	  DTH_TWRRD_MAX	   3
 #define  DTH_TWRWR_SHIFT   12
 #define  DTH_TWRWR_MASK    3
-#define   DTH_TWRWR_BASE   1 
+#define   DTH_TWRWR_BASE   1
 #define   DTH_TWRWR_MIN    1
 #define   DTH_TWRWR_MAX    3
 #define  DTH_TRDRD_SHIFT   14
@@ -167,7 +167,7 @@
 #define	  DTH_TREF_7_8_US  2
 #define	  DTH_TREF_3_9_US  3
 #define  DTH_TRFC0_SHIFT   20 /* for Logical DIMM0 */
-#define  DTH_TRFC_MASK      7  
+#define  DTH_TRFC_MASK      7
 #define	  DTH_TRFC_75_256M   0
 #define	  DTH_TRFC_105_512M  1
 #define   DTH_TRFC_127_5_1G  2
@@ -185,12 +185,12 @@
 #define   DCL_DramTerm_No   0
 #define   DCL_DramTerm_75_OH 1
 #define   DCL_DramTerm_150_OH 2
-#define   DCL_DramTerm_50_OH 3     
+#define   DCL_DramTerm_50_OH 3
 #define  DCL_DrvWeak	   (1<<7)
 #define  DCL_ParEn	   (1<<8)
 #define  DCL_SelfRefRateEn (1<<9)
 #define  DCL_BurstLength32 (1<<10)
-#define  DCL_Width128	   (1<<11) 
+#define  DCL_Width128	   (1<<11)
 #define  DCL_X4Dimm_SHIFT  12
 #define  DCL_X4Dimm_MASK   0xf
 #define  DCL_UnBuffDimm    (1<<16)
@@ -312,7 +312,7 @@
 #define  DATC_CkeFineDelay_MASK  0x1f
 #define   DATC_CkeFineDelay_BASE 0
 #define   DATC_CkeFineDelay_MIN  0
-#define   DATC_CkeFineDelay_MAX 31 
+#define   DATC_CkeFineDelay_MAX 31
 #define  DATC_CkeSetup	(1<<5)
 #define  DATC_CsOdtFineDelay_SHIFT 8
 #define  DATC_CsOdtFineDelay_MASK  0x1f
@@ -320,7 +320,7 @@
 #define   DATC_CsOdtFineDelay_MIN  0
 #define   DATC_CsOdtFineDelay_MAX 31
 #define  DATC_CsOdtSetup   (1<<13)
-#define  DATC_AddrCmdFineDelay_SHIFT 16 
+#define  DATC_AddrCmdFineDelay_SHIFT 16
 #define  DATC_AddrCmdFineDelay_MASK  0x1f
 #define   DATC_AddrCmdFineDelay_BASE 0
 #define   DATC_AddrCmdFineDelay_MIN  0
@@ -361,7 +361,7 @@
 #define DRAM_DQS_RECV_ENABLE_TIME2 0x16
 #define DRAM_DQS_RECV_ENABLE_TIME3 0x19
 
-/* there are index        0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x30, 0x33, 0x36, 0x39 
+/* there are index        0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x30, 0x33, 0x36, 0x39
 that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10, 0x13, 0x16, 0x19
 */
 #define DRAM_CTRL_MISC 0xa0
@@ -417,7 +417,7 @@ that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10,
 #define	  SCRUB_655_4us	   15
 #define	  SCRUB_1_31ms	   16
 #define	  SCRUB_2_62ms	   17
-#define	  SCRUB_5_24ms	   18 
+#define	  SCRUB_5_24ms	   18
 #define	  SCRUB_10_49ms	   19
 #define	  SCRUB_20_97ms	   20
 #define	  SCRUB_42ms	   21
@@ -530,7 +530,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 	unsigned needs_reset = 0;
 
 
-	if(sysinfo->nodes == 1) return; // in case only one cpu installed	
+	if(sysinfo->nodes == 1) return; // in case only one cpu installed
 
 	for(i=1; i<sysinfo->nodes; i++) {
 		/* Skip everything if I don't have any memory on this controller */
@@ -563,7 +563,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 #ifdef __PRE_RAM__
 		print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
 #else
-		printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); 
+		printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
 #endif
 		switch(sysinfo->mem_trained[i]) {
 		case 0: //don't need train
@@ -581,7 +581,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 		print_debug("mem trained failed\n");
 		soft_reset();
 #else
-		printk(BIOS_DEBUG, "mem trained failed\n"); 
+		printk(BIOS_DEBUG, "mem trained failed\n");
 		hard_reset();
 #endif
 	}
diff --git a/src/northbridge/amd/amdk8/exit_from_self.c b/src/northbridge/amd/amdk8/exit_from_self.c
index e42158d92a..13c72fe846 100644
--- a/src/northbridge/amd/amdk8/exit_from_self.c
+++ b/src/northbridge/amd/amdk8/exit_from_self.c
@@ -56,7 +56,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl,
 
 		printk(BIOS_DEBUG, "before resume errata #%d\n",
 			     (is_post_rev_g) ? 270 : 125);
-		/* 
+		/*
 		   1. Restore memory controller registers as normal.
 		   2. Set the DisAutoRefresh bit (Dev:2x8C[18]). (270 only)
 		   3. Set the EnDramInit bit (Dev:2x7C[31]), clear all other bits in the same register).
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index 18b3109cf6..5d51f036cb 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -4,7 +4,7 @@
  * devices which is done by the kernel
  *
  * written in 2003 by Eric Biederman
- * 
+ *
  *  - Athlon64 workarounds by Stefan Reinauer
  *  - "reset once" logic by Yinghai Lu
  */
@@ -24,7 +24,7 @@
 /**
  * @brief Read resources for AGP aperture
  *
- * @param 
+ * @param
  *
  * There is only one AGP aperture resource needed. The resoruce is added to
  * the northbridge of BSP.
@@ -64,7 +64,7 @@ static void mcf3_read_resources(device_t dev)
 static void set_agp_aperture(device_t dev)
 {
 	struct resource *resource;
-		
+
 	resource = probe_resource(dev, 0x94);
 	if (resource) {
 		device_t pdev;
@@ -78,7 +78,7 @@ static void set_agp_aperture(device_t dev)
 
 		/* Get the base address */
 		gart_base = ((resource->base) >> 25) & 0x00007fff;
-		
+
 		/* Update the other northbriges */
 		pdev = 0;
 		while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
@@ -90,7 +90,7 @@ static void set_agp_aperture(device_t dev)
 
 			/* Don't set the GART Table base address */
 			pci_write_config32(pdev, 0x98, 0);
-			
+
 			/* Report the resource has been stored... */
 			report_resource_stored(pdev, resource, " <gart>");
 		}
@@ -111,7 +111,7 @@ static void misc_control_init(struct device *dev)
 	uint32_t cmd, cmd_ref;
 	int needs_reset;
 	struct device *f0_dev;
-	
+
 	printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
 	needs_reset = 0;
 
@@ -125,7 +125,7 @@ static void misc_control_init(struct device *dev)
 	if (is_cpu_pre_c0()) {
 
 		/* Errata 58
-		 * Disable CPU low power states C2, C1 and throttling 
+		 * Disable CPU low power states C2, C1 and throttling
 		 */
 		cmd = pci_read_config32(dev, 0x80);
 		cmd &= ~(1<<0);
@@ -136,7 +136,7 @@ static void misc_control_init(struct device *dev)
 		pci_write_config32(dev, 0x84, cmd );
 
 		/* Errata 66
-		 * Limit the number of downstream posted requests to 1 
+		 * Limit the number of downstream posted requests to 1
 		 */
 		cmd = pci_read_config32(dev, 0x70);
 		if ((cmd & (3 << 0)) != 2) {
@@ -164,7 +164,7 @@ static void misc_control_init(struct device *dev)
 		struct device *f2_dev;
 		uint32_t dcl;
 		f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2);
-		/* Errata 98 
+		/* Errata 98
 		 * Set Clk Ramp Hystersis to 7
 		 * Clock Power/Timing Low
 		 */
@@ -192,7 +192,7 @@ static void misc_control_init(struct device *dev)
 			reg = 0x98 + (link * 0x20);
 			link_type = pci_read_config32(f0_dev, reg);
 			/* Only handle coherent link here please */
-			if ((link_type & (LinkConnected|InitComplete|NonCoherent)) 
+			if ((link_type & (LinkConnected|InitComplete|NonCoherent))
 				== (LinkConnected|InitComplete))
 			{
 				cmd &= ~(0xff << (link *8));
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index ad257d0ed6..7ad1b8004c 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -567,7 +567,7 @@ static int is_opteron(const struct mem_controller *ctrl)
 {
 	/* Test to see if I am an Opteron.  Socket 939 based Athlon64
 	 * have dual channel capability, too, so we need a better test
-	 * for Opterons. 
+	 * for Opterons.
 	 * However, all code uses is_opteron() to find out whether to
 	 * use dual channel, so if we really check for opteron here, we
 	 * need to fix up all code using this function, too.
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 6872883416..b89aa38d6a 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -393,7 +393,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
 	 *	   110 = 8 bus clocks
 	 *	   111 = 9 bus clocks
 	 * [ 7: 7] Reserved
-	 * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay, 
+	 * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay,
 	 * minium write-to-read delay when both access the same chip select)
 	 *	   00 = Reserved
 	 *	   01 = 1 bus clocks
@@ -525,7 +525,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
 	 *	       registered DIMM is present
 	 * [19:19] Reserved
 	 * [20:20] SlowAccessMode (Slow Access Mode (2T Mode))
-	 *	   0 = DRAM address and control signals are driven for one 
+	 *	   0 = DRAM address and control signals are driven for one
 	 *	       MEMCLK cycle
 	 *	   1 = One additional MEMCLK of setup time is provided on all
 	 *	       DRAM address and control signals except CS, CKE, and ODT;
@@ -720,7 +720,7 @@ static int is_opteron(const struct mem_controller *ctrl)
 {
 	/* Test to see if I am an Opteron. M2 and S1G1 support dual
 	 * channel, too, but only support unbuffered DIMMs so we need a
-	 * better test for Opterons. 
+	 * better test for Opterons.
 	 * However, all code uses is_opteron() to find out whether to
 	 * use dual channel, so if we really check for opteron here, we
 	 * need to fix up all code using this function, too.
@@ -1221,7 +1221,7 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl)
 			csbase = value;
 			canidate = index;
 		}
-		
+
 		/* See if I have found a new canidate */
 		if (csbase == 0) {
 			break;
@@ -1640,7 +1640,7 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor)
 	  /*15*/   200, 160, 120, 100,
 	};
 
-	
+
 	int index;
 	msr_t msr;
 
@@ -1659,7 +1659,7 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor)
 		unsigned fid_start;
 		msr = rdmsr(0xc0010015);
 		fid_start = (msr.lo & (0x3f << 24));
-		
+
 		index = fid_start>>25;
 	}
 
@@ -1843,7 +1843,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
 				continue;
 			}
 		}
-		
+
 	}
 	/* Make a second pass through the dimms and disable
 	 * any that cannot support the selected memclk and cas latency.
@@ -2060,7 +2060,7 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me
 	if (clocks < TT_MIN) {
 		clocks = TT_MIN;
 	}
-	
+
 	if (clocks > TT_MAX) {
 		printk(BIOS_INFO, "warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX);
 		clocks = TT_MAX;
@@ -3001,7 +3001,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 #else
 	int suspend = 0;
 #endif
- 
+
 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
 	 unsigned cpu_f0_f1[8];
 	/* FIXME: How about 32 node machine later? */
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 7b453bfc09..c56e51deb0 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -436,7 +436,7 @@ static uint16_t get_exact_T1000(unsigned i)
 		unsigned fid_start;
 		msr = rdmsr(0xc0010015);
 		fid_start = (msr.lo & (0x3f << 24));
-		
+
 		index = fid_start>>25;
 	}
 
@@ -600,12 +600,12 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
 	}
 
 	for ( ; (channel < 2) && (!Errors); channel++)
-	{ 
-		print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1); 
-		
-		/* for each rank */ 
-		/* there are four recriver pairs, loosely associated with CS */ 
-		for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) 
+	{
+		print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1);
+
+		/* for each rank */
+		/* there are four recriver pairs, loosely associated with CS */
+		for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2)
 		{
 
 			unsigned index=(receiver>>1) * 3 + 0x10;
diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c
index 042bc9949b..82622cdc4c 100644
--- a/src/northbridge/amd/amdk8/setup_resource_map.c
+++ b/src/northbridge/amd/amdk8/setup_resource_map.c
@@ -231,7 +231,7 @@ static void setup_mem_resource_map(const unsigned int *register_values, int max)
 		unsigned where;
 		unsigned long reg;
 #if 0
-		prink(BIOS_DEBUG, "%08x <-  %08x\n", 
+		prink(BIOS_DEBUG, "%08x <-  %08x\n",
 			register_values[i], register_values[i+2]);
 #endif
 		where = register_values[i];
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index fe4ae8c30c..3c4fa89e89 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -3391,7 +3391,7 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat,
 	u8 max_dimms;
 
 	// FIXME: skip for Ax
-	
+
 	dev = pDCTstat->dev_dct;
 
 	/* Tri-state unused ODTs when motherboard termination is available */
diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c
index 1b0214d9fd..1176744c87 100644
--- a/src/northbridge/amd/gx1/northbridge.c
+++ b/src/northbridge/amd/gx1/northbridge.c
@@ -40,10 +40,10 @@ static void enable_shadow(device_t dev)
        write32(GX_BASE+BC_XMAP_3, 0x77777777);
 }
 
-static void northbridge_init(device_t dev) 
+static void northbridge_init(device_t dev)
 {
 	printk(BIOS_DEBUG, "northbridge: %s()\n", __func__);
-	
+
 	optimize_xbus(dev);
 	enable_shadow(dev);
 	printk(BIOS_SPEW, "Calling enable_cache()\n");
@@ -63,7 +63,7 @@ static struct device_operations northbridge_operations = {
 static const struct pci_driver northbridge_driver __pci_driver = {
 	.ops = &northbridge_operations,
 	.vendor = PCI_VENDOR_ID_CYRIX,
-	.device = PCI_DEVICE_ID_CYRIX_PCI_MASTER, 
+	.device = PCI_DEVICE_ID_CYRIX_PCI_MASTER,
 };
 
 static void ram_resource(device_t dev, unsigned long index,
@@ -132,7 +132,7 @@ static void pci_domain_set_resources(device_t dev)
 				continue;
 			ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
 		}
-			
+
 		tomk = ramreg << 10;
 
 		/* Sort out the framebuffer size */
@@ -172,7 +172,7 @@ static struct device_operations pci_domain_ops = {
         .enable_resources = enable_childrens_resources,
         .init             = 0,
         .scan_bus         = pci_domain_scan_bus,
-};  
+};
 
 static void cpu_bus_init(device_t dev)
 {
@@ -211,5 +211,5 @@ static void enable_dev(struct device *dev)
 
 struct chip_operations northbridge_amd_gx1_ops = {
 	CHIP_NAME("AMD GX1 Northbridge")
-	.enable_dev = enable_dev, 
+	.enable_dev = enable_dev,
 };
diff --git a/src/northbridge/amd/gx1/raminit.c b/src/northbridge/amd/gx1/raminit.c
index f61a69b4f8..8525ce4d1f 100644
--- a/src/northbridge/amd/gx1/raminit.c
+++ b/src/northbridge/amd/gx1/raminit.c
@@ -12,7 +12,7 @@ U.S. Government has rights to use, reproduce, and distribute this
 SOFTWARE.  The public may copy, distribute, prepare derivative works
 and publicly display this SOFTWARE without charge, provided that this
 Notice and any statement of authorship are reproduced on all copies.
-Neither the Government nor the University makes any warranty, express 
+Neither the Government nor the University makes any warranty, express
 or implied, or assumes any liability or responsibility for the use of
 this SOFTWARE.  If SOFTWARE is modified to produce derivative works,
 such modified SOFTWARE should be clearly marked, so as not to confuse
@@ -22,7 +22,7 @@ it with the version available from LANL.
  * rminnich@lanl.gov
  */
 
-/* 	SDRAM initialization for GX1 - translated from Christer Weinigel's 
+/* 	SDRAM initialization for GX1 - translated from Christer Weinigel's
 	assembler version into C.
 
 	Hamish Guthrie 10/4/2005 hamish@prodigi.ch
@@ -53,7 +53,7 @@ unsigned int tval, i;
 		setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
 	outb(0x72, 0x80);
 }
-	
+
 
 void enable_dimm(void)
 {
@@ -93,12 +93,12 @@ unsigned int tval, i;
 	tval &= ~PROGRAM_SDRAM;
 	setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
 
-	/* Refresh memory again */	
+	/* Refresh memory again */
 	tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1);
 	tval |= RFSHTST;
 	for(i=0; i>NUM_REFRESH; i++)
 		setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
-	
+
 	for(i=0; i<2000; i++)
 		outb(0, 0xed);
 	outb(0x74, 0x80);
@@ -132,7 +132,7 @@ int failed_flag = 1;
 		return (0x0070 << dimm_shift);
 	else
 		return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_SZ << dimm_shift));
-		
+
 }
 
 static unsigned int module_banks(int dimm_shift)
@@ -229,7 +229,7 @@ unsigned int probe_config;
 #endif
 			return(page_size_config << dimm_shift);
 			}
-		
+
 		temp = ~(DIMM_PG_SZ << dimm_shift);
 
 		probe_config = getGX1Mem(GX_BASE + MC_BANK_CFG);
@@ -300,23 +300,23 @@ static int size_memory(int dimm_shift, unsigned int mem_config)
 
 	mem_config &= (~(DIMM_MOD_BNK << dimm_shift));
 	mem_config |= (module_banks(dimm_shift));
-	
+
 	print_debug("    Module Banks:    ");
 	print_debug_char((((mem_config & (DIMM_MOD_BNK << dimm_shift)) >> (dimm_shift + 14)) ? 2 : 1) + 0x30);
 	print_debug("\n");
 
 	mem_config &= (~(DIMM_SZ << dimm_shift));
 	mem_config |= (size_dimm(dimm_shift));
-	
+
 	print_debug("    DIMM size:       ");
-	print_debug_hex32(1 << 
+	print_debug_hex32(1 <<
 		((mem_config & (DIMM_SZ << dimm_shift)) >> (dimm_shift + 8)) + 22);
 	print_debug("\n");
 
 	return (mem_config);
 }
 
-static void sdram_init(void) 
+static void sdram_init(void)
 {
 unsigned int mem_config = 0x00700070;
 
@@ -327,7 +327,7 @@ unsigned int mem_config = 0x00700070;
 	setGX1Mem(GX_BASE + MC_MEM_CNTRL1, 0x92140000); /* MD_DS=2, MA_DS=2, CNTL_DS=2 SDCLKRATE=4 */
 	setGX1Mem(GX_BASE + MC_BANK_CFG,   0x00700070); /* No DIMMS installed */
 	setGX1Mem(GX_BASE + MC_SYNC_TIM1,  0x3a733225); /* LTMODE=3, RC=10, RAS=7, RP=3, RCD=3, RRD=2, DPL=2 */
-	setGX1Mem(GX_BASE + MC_BANK_CFG,   0x57405740); /* Largest DIMM size 
+	setGX1Mem(GX_BASE + MC_BANK_CFG,   0x57405740); /* Largest DIMM size
 						0x4000 -- 2 module banks
 						0x1000 -- 4 component banks
 						0x0700 -- DIMM size 512MB
diff --git a/src/northbridge/amd/gx2/chipsetinit.c b/src/northbridge/amd/gx2/chipsetinit.c
index 620f56452d..f0b99e7e9d 100644
--- a/src/northbridge/amd/gx2/chipsetinit.c
+++ b/src/northbridge/amd/gx2/chipsetinit.c
@@ -61,7 +61,7 @@ static struct msrinit CS5536_CLOCK_GATING_TABLE[] = {
 
 #ifdef UNUSED_CODE
 struct acpiinit {
-	unsigned short ioreg; 
+	unsigned short ioreg;
 	unsigned long regdata;
 	unsigned short iolen;
 };
@@ -116,21 +116,21 @@ static void pmChipsetInit(void)
 	port =  (PMLogic_BASE + 0x034);
 	val =  0x0A0		; /*  5ms*/
 	outl(val, port);
-	
+
 	/*  PM_WKD*/
 	port =  (PMLogic_BASE + 0x030);
 	outl(val, port);
-		
+
 	/*  PM_SED*/
 	port =  (PMLogic_BASE + 0x014);
 	val =  0x04601		; /*  5ms*/
 	outl(val, port);
-	
+
 	/*  PM_SIDD*/
 	port =  (PMLogic_BASE + 0x020);
 	val =  0x08C02		; /*  10ms*/
 	outl(val, port);
-	
+
 	/* GPIO24 OUT_AUX1 function is the external signal for 5535's
 	 * vsb_working_aux which is de-asserted when 5535 enters Standby (S3 or
 	 * S5) state.  On Hawk, GPIO24 controls all voltage rails except Vmem
@@ -154,7 +154,7 @@ static void pmChipsetInit(void)
 	 * Programming of GPIO11 will be done by VSA PM code.  During VSA
 	 * Init. BIOS writes PM Core Virual Register indicating if S1 Clocks
 	 * should be On or Off. This is based on a Setup item.  We do not want
-	 * to leave GPIO11 enabled because of a Hawk board problem.  With 
+	 * to leave GPIO11 enabled because of a Hawk board problem.  With
 	 * GPIO11 enabled in S3, something is back-driving GPIO11 causing it
 	 * to float to 1.6-1.7V.
 	 */
@@ -188,7 +188,7 @@ static uint32_t FlashPort[] = {
  *	ChipsetFlashSetup
  *
  *	Flash LBARs need to be setup before VSA init so the PCI BARs have
- *	correct size info.  Call this routine only if flash needs to be 
+ *	correct size info.  Call this routine only if flash needs to be
  *	configured (don't call it if you want IDE).
  *
  **************************************************************************/
@@ -240,16 +240,16 @@ static void ChipsetFlashSetup(void)
 }
 
 
- 
+
 /****************************************************************************
- * 
+ *
  * 	ChipsetGeodeLinkInit
  *
  * 	Handle chipset specific GeodeLink settings here.
  * 	Called from GeodeLink init code.
- * 
+ *
  ****************************************************************************/
-static void 
+static void
 ChipsetGeodeLinkInit(void)
 {
 	msr_t msr;
@@ -269,7 +269,7 @@ ChipsetGeodeLinkInit(void)
 		return;
 
 	totalmem = sizeram() << 20 - 1;
-	totalmem >>= 12; 
+	totalmem >>= 12;
 	totalmem = ~totalmem;
 	totalmem &= 0xfffff;
 	msr.lo = totalmem;
@@ -292,7 +292,7 @@ gx2_chipsetinit (struct northbridge_amd_gx2_config *nb)
 	printk(BIOS_DEBUG, "Companion is a %s\n", is_5536()?"CS5536":"CS5535");
 
 #ifdef UNUSED_CODE
-	/* we hope NEVER to be in coreboot when S3 resumes 
+	/* we hope NEVER to be in coreboot when S3 resumes
 	if (! IsS3Resume()) */
 	{
 		struct acpiinit *aci = acpi_init_table;
@@ -319,14 +319,14 @@ gx2_chipsetinit (struct northbridge_amd_gx2_config *nb)
 		msrnum = MSR_SB_USB2 + 8;
 		wrmsr(msrnum, msr);
 	}
-	
+
 	/* set hd IRQ */
 	outl	(GPIOL_2_SET, GPIOL_INPUT_ENABLE);
 	outl	(GPIOL_2_SET, GPIOL_IN_AUX1_SELECT);
 
 	/*  Allow IO read and writes during a ATA DMA operation. */
 	/*   This could be done in the HD rom but do it here for easier debugging. */
-	
+
 	msrnum = ATA_SB_GLD_MSR_ERR;
 	msr = rdmsr(msrnum);
 	msr.lo &= ~0x100;
diff --git a/src/northbridge/amd/gx2/grphinit.c b/src/northbridge/amd/gx2/grphinit.c
index a30ba78373..e59a838afe 100644
--- a/src/northbridge/amd/gx2/grphinit.c
+++ b/src/northbridge/amd/gx2/grphinit.c
@@ -4,7 +4,7 @@
 #include <device/device.h>
 #include "chip.h"
 #include "northbridge.h"
- 
+
 // FIXME handle UMA properly.
 #define VIDEO_MB	8					// MB of video memory
 
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index e74a8e33f8..98acbc9f95 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -19,7 +19,7 @@
 
 #define NORTHBRIDGE_FILE "northbridge.c"
 
-/* todo: add a resource record. We don't do this here because this may be called when 
+/* todo: add a resource record. We don't do this here because this may be called when
   * very little of the platform is actually working.
   */
 int
@@ -128,7 +128,7 @@ static void irq_init_steering(struct device *dev, u16 irq_map) {
 	printk(BIOS_DEBUG, "%s(%p [%08X], %04X)\n", __func__, dev, pciAddr, irq_map);
 
 	/* The IRQ steering values (in hex) are effectively dcba, where:
-	 *    <a> represents the IRQ for INTA, 
+	 *    <a> represents the IRQ for INTA,
 	 *    <b> represents the IRQ for INTB,
 	 *    <c> represents the IRQ for INTC, and
 	 *    <d> represents the IRQ for INTD.
@@ -146,10 +146,10 @@ static void irq_init_steering(struct device *dev, u16 irq_map) {
 /*
  * setup_gx2_cache
  *
- * Returns the amount of memory (in KB) available to the system.  This is the 
+ * Returns the amount of memory (in KB) available to the system.  This is the
  * total amount of memory less the amount of memory reserved for SMM use.
  *
- */ 
+ */
 static int
 setup_gx2_cache(void)
 {
@@ -200,13 +200,13 @@ setup_gx2(void)
 
 	membytes = size_kb * 1024;
 	/* NOTE! setup_gx2_cache returns the SIZE OF RAM - RAMADJUST!
-	  * so it is safe to use. You should NOT at this point call 	
-	  * sizeram() directly. 
+	  * so it is safe to use. You should NOT at this point call
+	  * sizeram() directly.
 	  */
 
 	/* we need to set 0x10000028 and 0x40000029 */
 	/*
-	 * These two descriptors cover the range from 1 MB (0x100000) to 
+	 * These two descriptors cover the range from 1 MB (0x100000) to
 	 * SYSTOP (a.k.a. TOM, or Top of Memory)
 	 */
 
@@ -271,16 +271,16 @@ setup_gx2(void)
 
 static void enable_shadow(device_t dev)
 {
-	
+
 }
 
-static void northbridge_init(device_t dev) 
+static void northbridge_init(device_t dev)
 {
 	unsigned long m;
 
 	struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
 	printk(BIOS_DEBUG, "northbridge: %s()\n", __func__);
-	
+
 	enable_shadow(dev);
 	irq_init_steering(dev, nb->irqmap);
 
@@ -421,7 +421,7 @@ static void pci_domain_set_resources(device_t dev)
 				continue;
 			ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
 		}
-			
+
 		tomk = ramreg << 10;
 
 		/* Sort out the framebuffer size */
@@ -455,7 +455,7 @@ static struct device_operations pci_domain_ops = {
         .enable_resources = enable_childrens_resources,
         .init             = 0,
         .scan_bus         = pci_domain_scan_bus,
-};  
+};
 
 static void cpu_bus_init(device_t dev)
 {
@@ -516,5 +516,5 @@ static void enable_dev(struct device *dev)
 
 struct chip_operations northbridge_amd_gx2_ops = {
 	CHIP_NAME("AMD GX (previously GX2) Northbridge")
-	.enable_dev = enable_dev, 
+	.enable_dev = enable_dev,
 };
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index 4ad5af23bc..7053f5e5d9 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -126,14 +126,14 @@ ShadowInit(struct gliutable *gl)
 	msr = rdmsr(gl->desc_name);
 
 	if (msr.lo == 0) {
-		writeglmsr(gl); 
+		writeglmsr(gl);
 	}
 }
 
-/* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here. 
+/* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here.
   * CLEAN ME UP
    */
-/* yes, this duplicates later code, but it seems that is how they want it done. 
+/* yes, this duplicates later code, but it seems that is how they want it done.
   */
 static void
 SysmemInit(struct gliutable *gl)
@@ -141,8 +141,8 @@ SysmemInit(struct gliutable *gl)
 	msr_t msr;
 	int sizembytes, sizebytes;
 
-	/* 
-	 * Figure out how much RAM is in the machine and alocate all to the 
+	/*
+	 * Figure out how much RAM is in the machine and alocate all to the
 	 * system. We will adjust for SMM and DMM now and Frame Buffer later.
 	 */
 	sizembytes = sizeram();
@@ -165,7 +165,7 @@ SysmemInit(struct gliutable *gl)
 	msr = rdmsr(gl->desc_name);
 	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__,
 				gl->desc_name, msr.hi, msr.lo);
-	
+
 }
 static void
 DMMGL0Init(struct gliutable *gl) {
@@ -188,11 +188,11 @@ DMMGL0Init(struct gliutable *gl) {
 	msr.hi |= (DMM_OFFSET >> 24);
 	msr.lo = DMM_OFFSET << 8;
 	msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
-	
+
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
 	msr = rdmsr(gl->desc_name);
 	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
-	
+
 }
 static void
 DMMGL1Init(struct gliutable *gl) {
@@ -211,7 +211,7 @@ DMMGL1Init(struct gliutable *gl) {
 	/* hmm. AMD source has SMM here ... SMM, not DMM? We think DMM */
 	printk(BIOS_ERR, "%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__);
 	msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
-	
+
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
 	msr = rdmsr(gl->desc_name);
 	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
@@ -238,7 +238,7 @@ SMMGL0Init(struct gliutable *gl) {
 
 	msr.lo = SMM_OFFSET << 8;
 	msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
-	
+
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
 	msr = rdmsr(gl->desc_name);
 	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
@@ -254,7 +254,7 @@ SMMGL1Init(struct gliutable *gl) {
 	msr.hi |= (SMM_OFFSET >> 24);
 	msr.lo = SMM_OFFSET << 8;
 	msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
-	
+
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
 	msr = rdmsr(gl->desc_name);
 	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
@@ -265,31 +265,31 @@ GLIUInit(struct gliutable *gl){
 
 	while (gl->desc_type != GL_END){
 		switch(gl->desc_type){
-		default: 
+		default:
 			/* For Unknown types: Write then read MSR */
 			writeglmsr(gl);
 		case SC_SHADOW: /*  Check for a Shadow entry*/
 			ShadowInit(gl);
 			break;
-	
+
 		case R_SYSMEM: /*  check for a SYSMEM entry*/
 			SysmemInit(gl);
 			break;
-	
+
 		case BMO_DMM: /*  check for a DMM entry*/
 			DMMGL0Init(gl);
 			break;
-	
+
 		case BM_DMM	: /*  check for a DMM entry*/
 			DMMGL1Init(gl);
 			break;
-	
+
 		case BMO_SMM	: /*  check for a SMM entry*/
 			SMMGL0Init(gl);
 			break;
-	
+
 		case BM_SMM	: /*  check for a SMM entry*/
-			SMMGL1Init(gl);	
+			SMMGL1Init(gl);
 			break;
 		}
 		gl++;
@@ -413,7 +413,7 @@ static void GLPCIInit(void){
 
 	/* */
 	/* 5535 NB Init*/
-	/* */	
+	/* */
 	msrnum = GLPCI_ARB;
 	msr = rdmsr(msrnum);
 	msr.hi |=  GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET;
@@ -432,19 +432,19 @@ static void GLPCIInit(void){
 
 	msr.lo &=  ~ (0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT);
 	msr.lo |=  0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT;
-	
+
 	msr.hi &=  ~ (0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT);
 	msr.hi |=  0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT;
-	
+
 	msr.hi &=  ~ (0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT);
 	msr.hi |=  0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT;
-	
+
 	msr.hi &=  ~ (0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT);
 	msr.hi |=  0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT;
-	
+
 	msr.hi &=  ~ (0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT);
 	msr.hi |=  0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT;
-	
+
 	msr.hi &=  ~ (0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT);
 	msr.hi |=  0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT;
 	wrmsr(msrnum, msr);
@@ -478,7 +478,7 @@ static void GLPCIInit(void){
 	/* *	Modified:*/
 	/* **/
 	/* ***************************************************************************/
-static void 
+static void
 ClockGatingInit (void){
 	msr_t msr;
 	struct msrinit *gating = ClockGatingDefault;
@@ -489,7 +489,7 @@ ClockGatingInit (void){
 	NOSTACK	bx, GetNVRAMValueBX
 	cmp	al, TVALUE_CG_OFF
 	je	gatingdone
-	
+
 	cmp	al, TVALUE_CG_DEFAULT
 	jb	allon
 	ja	performance
@@ -517,7 +517,7 @@ performance:
 
 }
 
-static void 
+static void
 GeodeLinkPriority(void){
 	msr_t msr;
 	struct msrinit *prio = GeodeLinkPriorityTable;
@@ -537,7 +537,7 @@ GeodeLinkPriority(void){
 }
 
 
-	
+
 /*
  *	Get the GLIU0 shadow register settings
  *	If the setShadow function is used then all shadow descriptors
@@ -613,7 +613,7 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
 static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo)
 {
 	msr_t msr;
-	
+
 // Set the Enable Register.
 
 	msr = rdmsr(GLPCI_REN);
@@ -667,7 +667,7 @@ static void setShadow(uint64_t shadowSettings)
  *	Destroys:
  *
  **************************************************************************/
-static void 
+static void
 shadowRom(void)
 {
 	uint64_t shadowSettings = getShadow();
@@ -688,7 +688,7 @@ shadowRom(void)
  *  ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area
  *  DEVRC(35:28) =  39h	 ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
  *  SYSTOP(27:8) = top of system memory
- *  SYSRC(7:0) = 00h 		 ; writeback, can set to 08h to make writethrough 
+ *  SYSRC(7:0) = 00h 		 ; writeback, can set to 08h to make writethrough
  *
  ***************************************************************************/
 #define SYSMEM_RCONF_WRITETHROUGH 8
@@ -716,17 +716,17 @@ RCONFInit(void)
 		while (1);
 	}
 
-// sysdescfound:	
+// sysdescfound:
 	/* found the descriptor... get its contents */
 	msr = rdmsr(gl->desc_name);
 
-	/* 20 bit address -  The bottom 12 bits go into bits 20-31 in eax, the 
-	 * top 8 bits go into 0-7 of edx. 
+	/* 20 bit address -  The bottom 12 bits go into bits 20-31 in eax, the
+	 * top 8 bits go into 0-7 of edx.
 	 */
 	msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF);
 	msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF;
 	msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT;	// 8
-	
+
 	// Set Default SYSMEM region properties
 	msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH;	// 8 (or ~8)
 
@@ -739,7 +739,7 @@ RCONFInit(void)
 
 	// Set ROMBASE cache properties.
 	msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24));
-	
+
 	// now program RCONF_DEFAULT
 	wrmsr(CPU_RCONF_DEFAULT, msr);
 
@@ -776,15 +776,15 @@ northbridgeinit(void)
 		GLIUInit(gliutables[i]);
 
 	GeodeLinkPriority();
-	
+
 	shadowRom();
-	
-	// GeodeROM ensures that the BIOS waits the required 1 second before 
+
+	// GeodeROM ensures that the BIOS waits the required 1 second before
 	// allowing anything to access PCI
 	// PCIDelay();
-	
+
 	RCONFInit();
-	
+
 	// The cacheInit function in GeodeROM tests cache and, among other things,
 	// makes sure all INVD instructions are treated as WBINVD.  We do this
 	// because we've found some programs which require this behavior.
@@ -792,7 +792,7 @@ northbridgeinit(void)
 	msr = rdmsr(CPU_DM_CONFIG0);
 	msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;
 	wrmsr(CPU_DM_CONFIG0, msr);
-	
+
 	/*  Now that the descriptor to memory is set up.*/
 	/*  The memory controller needs one read to synch its lines before it can be used.*/
 	i = *(int *) 0;
diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c
index 898e31dcd4..c1b22a28a0 100644
--- a/src/northbridge/amd/gx2/pll_reset.c
+++ b/src/northbridge/amd/gx2/pll_reset.c
@@ -125,7 +125,7 @@ static unsigned int get_memory_speed(void)
 
 #define DEFAULT_MDIV	3
 #define DEFAULT_VDIV	2
-#define DEFAULT_FBDIV	22	// 366/244 ; 24 400/266 018 ;300/200 
+#define DEFAULT_FBDIV	22	// 366/244 ; 24 400/266 018 ;300/200
 
 static void pll_reset(void)
 {
@@ -134,10 +134,10 @@ static void pll_reset(void)
 	unsigned SyncBits;			// store the sync bits in up ebx
 
 	// clear the Bypass bit
-	
+
 	// If the straps say we are in bypass and the syspll is not AND there are no software
 	// bits set then FS2 or something set up the PLL and we should not change it.
-	
+
 	msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
 	msrGlcpSysRstpll.lo &= ~RSTPPL_LOWER_BYPASS_SET;
 	wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
@@ -145,15 +145,15 @@ static void pll_reset(void)
 	// If the "we've already been here" flag is set, don't reconfigure the pll
 	if ( !(msrGlcpSysRstpll.lo & PLLCHECK_COMPLETED ) )
 	{ // we haven't configured the PLL; do it now
-	
+
 		// Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the
 		// correct Strap Table.
 		post_code(POST_PLL_INIT);
-		
+
 		// configure for DDR
 		msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT);
 		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
-		
+
 		// Use Manual settings
 		//	UseManual:
 		post_code(POST_PLL_MANUAL);
@@ -161,7 +161,7 @@ static void pll_reset(void)
 		// DIV settings manually entered.
 		// ax = VDIV, upper eax = MDIV, upper ecx = FbDIV
 		// use gs and fs since we don't need them.
-		
+
 		//	ProgramClocks:
 		// ax = VDIV, upper eax = MDIV, upper ecx = FbDIV
 		// move everything into ebx
@@ -174,7 +174,7 @@ static void pll_reset(void)
 		// FbDIV
 		MDIV_VDIV_FBDIV |= (plldiv2fbdiv[DEFAULT_FBDIV] << RSTPLL_UPPER_FBDIV_SHIFT);
 
-		// write GLCP_SYS_RSTPPL (GLCP reg 0x14) with clock values  
+		// write GLCP_SYS_RSTPPL (GLCP reg 0x14) with clock values
 		msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT);
 		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
 
@@ -192,15 +192,15 @@ static void pll_reset(void)
 		// Check for Bypass mode.
 		if (msrGlcpSysRstpll.lo & RSTPPL_LOWER_BYPASS_SET)
 		{
-			// If we are in BYPASS PCI may or may not be sync'd but CPU and GeodeLink will.	
+			// If we are in BYPASS PCI may or may not be sync'd but CPU and GeodeLink will.
 			SyncBits |= RSTPPL_LOWER_CPU_SEMI_SYNC_SET;
 		}
 		else
 		{
-			//	CheckPCIsync:	
+			//	CheckPCIsync:
 			// If FBdiv/Mdiv is evenly divisible then set the PCI semi-sync. FB is always greater
 			// look up the real divider... if we get a 0 we have serious problems
-			if ( !(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] % 
+			if ( !(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] %
 				(((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x0F) + 2)) )
 			{
 				SyncBits |= RSTPPL_LOWER_PCI_SEMI_SYNC_SET;
@@ -234,13 +234,13 @@ static void pll_reset(void)
 		msrGlcpSysRstpll.lo |= (RSTPPL_LOWER_PLL_RESET_SET + RSTPPL_LOWER_PD_SET);
 		msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
 		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
-		
+
 		// You should never get here..... The chip has reset.
 		post_code(POST_PLL_RESET_FAIL);
 		while (1);
 
 	} // we haven't configured the PLL; do it now
-	
+
 }
 // End of Goodrich version of pll_reset
 ///////////////////////////////////////////////////////////////////////////////
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c
index b1cb1af6b3..3f99cab8ee 100644
--- a/src/northbridge/amd/gx2/raminit.c
+++ b/src/northbridge/amd/gx2/raminit.c
@@ -61,7 +61,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	//print_debug("sdram_enable step 6\n");
 
 	/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
-	 * it is documented in LX datasheet  */	
+	 * it is documented in LX datasheet  */
 	/* load Mode Register by set and clear PROG_DRAM */
 	msr = rdmsr(0x20000018);
 	msr.lo |=  ((0x01 << 27) | 0x01);
@@ -85,10 +85,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	/* load RDSYNC */
 	msr = rdmsr(0x2000001f);
 	msr.hi = 0x000ff310;
-	/* the above setting is supposed to be good for "slow" ram. We have found that for 
-	 * some dram, at some clock rates, e.g. hynix at 366/244, this will actually 
+	/* the above setting is supposed to be good for "slow" ram. We have found that for
+	 * some dram, at some clock rates, e.g. hynix at 366/244, this will actually
 	 * cause errors. The fix is to just set it to 0x310. Tested on 3 boards
-	 * with 3 different type of dram -- Hynix, PSC, infineon. 
+	 * with 3 different type of dram -- Hynix, PSC, infineon.
 	 * I am leaving this comment here so that at some future time nobody is tempted
 	 * to mess with this setting -- RGM, 9/2006
 	 */
diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig
index 57a485eedc..09eba0791a 100644
--- a/src/northbridge/amd/lx/Kconfig
+++ b/src/northbridge/amd/lx/Kconfig
@@ -2,7 +2,7 @@ config NORTHBRIDGE_AMD_LX
 	bool
 	select HAVE_HIGH_TABLES
 	select GEODE_VSA
-	
+
 config VIDEO_MB
 	int
 	default 8
diff --git a/src/northbridge/amd/lx/grphinit.c b/src/northbridge/amd/lx/grphinit.c
index 85e6a45ba0..b245eea062 100644
--- a/src/northbridge/amd/lx/grphinit.c
+++ b/src/northbridge/amd/lx/grphinit.c
@@ -35,7 +35,7 @@ struct msrinit {
 };
 
 static const struct msrinit geodelx_vga_msr[] = {
-	/* Enable the GLIU Memory routing to the hardware 
+	/* Enable the GLIU Memory routing to the hardware
 	* PDID1 : Port 4, GLIU0
 	* PBASE : 0x000A0
 	* PMASK : 0xFFFE0
@@ -71,9 +71,9 @@ void graphics_init(void)
 
 	/* SoftVG initialization */
 	printk(BIOS_DEBUG, "Graphics init...\n");
-   
+
 	geodelx_vga_msr_init();
-   
+
 	/* Call SoftVG with the main configuration parameters. */
 	/* NOTE: SoftVG expects the memory size to be given in 2MB blocks */
 
@@ -94,7 +94,7 @@ void graphics_init(void)
 	 *   so we can add the real value in megabytes
 	 */
 
-	wData = VG_CFG_DRIVER | VG_CFG_PRIORITY | 
+	wData = VG_CFG_DRIVER | VG_CFG_PRIORITY |
 			VG_CFG_DSCRT | (CONFIG_VIDEO_MB & VG_MEM_MASK);
 	vrWrite(wClassIndex, wData);
 
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index 4dd29d134f..6eba99d9df 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -262,7 +262,7 @@ void print_conf(void)
 #endif				//CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
 }
 
-/* todo: add a resource record. We don't do this here because this may be called when 
+/* todo: add a resource record. We don't do this here because this may be called when
   * very little of the platform is actually working.
   */
 int sizeram(void)
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index 75d77f0305..9014fb1de3 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -22,9 +22,9 @@
 #include <spd.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 
-static const unsigned char NumColAddr[] = { 
-	0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07, 
-	0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F 
+static const unsigned char NumColAddr[] = {
+	0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,
+	0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
 };
 
 static void banner(const char *s)
@@ -35,8 +35,8 @@ static void banner(const char *s)
 static void hcf(void)
 {
 	print_emerg("DIE\n");
-	/* this guarantees we flush the UART fifos (if any) and also 
-	 * ensures that things, in general, keep going so no debug output 
+	/* this guarantees we flush the UART fifos (if any) and also
+	 * ensures that things, in general, keep going so no debug output
 	 * is lost
 	 */
 	while (1)
@@ -231,7 +231,7 @@ static void set_refresh_rate(void)
 	}
 
 	msr = rdmsr(MC_CF07_DATA);
-	msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16) 
+	msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16)
 			<< CF07_LOWER_REF_INT_SHIFT;
 	wrmsr(MC_CF07_DATA, msr);
 }
@@ -649,7 +649,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	/* If both Page Size = "Not Installed" we have a problems and should halt. */
 	msr = rdmsr(MC_CF07_DATA);
-	if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) == 
+	if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
 			((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
 		print_emerg("No memory in the system\n");
 		post_code(ERROR_NO_DIMMS);