summaryrefslogtreecommitdiff
path: root/src/northbridge/amd
diff options
context:
space:
mode:
authorMarshall Dawson <marshall.dawson@scarletltd.com>2018-05-07 08:51:04 -0600
committerMartin Roth <martinroth@google.com>2018-06-13 21:20:41 +0000
commit10b52e0f2265aa978b0b2599504b1c818943f521 (patch)
tree3a97b4256b484e9e20cdcab80c7c974b6d504fa6 /src/northbridge/amd
parent669ba237100da680fb56950feab2b6591218e184 (diff)
amd/pi: Add GetTempHeapBase callout
Implement a new AGESA callout that may be used to find the correct temporary location in DRAM to store heap data. Near the end of AmdInitPost, AGESA migrates its heap from a CAR-based location to a temporary region. Once cbmem has been established, the heap will be relocated again in AmdInitEnv from the temp location to the final one. This patch does not materially affect the behavior of AGESA's heap management. It only puts coreboot in control of the location. Future work may refactor the copying. TEST=Boot grunt with patchstack and experimental blob BUG=b:74518368 Change-Id: Ibc5cc988e3e80d78f50cf0195e952b657141e570 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd')
0 files changed, 0 insertions, 0 deletions